Design of a simulation platform to test next generation of terrestrial DVB

Digital Terrestrial Television Broadcasting (DTTB) is a member of our daily life routine, and nonetheless, according to new users’ necessities in the fields of communications and leisure, new challenges are coming up. Moreover, the current Standard is not able to satisfy all the potential requirements. For that reason, first of all, a review of the current Standard has been performed within this work. Then, it has been identified the needing of developing a new version of the standard, ready to support enhanced services, as for example broadcasting transmissions to moving terminals or High Definition Television (HDTV) transmissions, among others. The main objective of this project is the design and development of a physical layer simulator of the whole DVB-T standard, including both the complete transmission and reception procedures. The simulator has been developed in Matlab. A detailed description of the simulator both from a functional and an architectural point of view is included. The simulator is the base for testing any possible modifications that may be included into the DVB-T2 future standard. In fact, several proposed enhancements have already been carried out and their performance has been evaluated. Specifically, the use of higher order modulation schemes, and the corresponding modifications in all the system blocks, have been included and evaluated. Furthermore, the simulator will allow testing other enhancements as the use of more efficient encoders and interleavers, MIMO technologies, and so on. A complete set of numerical results showing the performance of the different parts of the system, are presented in order to validate the correctness of the implementation and to evaluate both the current standard performance and the proposed enhancements. This work has been performed within the context of a project called FURIA, which is a strategic research project funded by the Spanish Ministry of Industry, Tourism and Commerce. A brief description of this project and its consortium has been also included herein, together with an introduction to the current situation of the DTTB in Spain (called TDT in Spanish)

Design of a simulation platform to test next generation of terrestrial DVB

Digital Terrestrial Television Broadcasting (DTTB) is a member of our daily life routine, and nonetheless, according to new users’ necessities in the fields of communications and leisure, new challenges are coming up. Moreover, the current Standard is not able to satisfy all the potential requirements. For that reason, first of all, a review of the current Standard has been performed within this work. Then, it has been identified the needing of developing a new version of the standard, ready to support enhanced services, as for example broadcasting transmissions to moving terminals or High Definition Television (HDTV) transmissions, among others. The main objective of this project is the design and development of a physical layer simulator of the whole DVB-T standard, including both the complete transmission and reception procedures. The simulator has been developed in Matlab. A detailed description of the simulator both from a functional and an architectural point of view is included. The simulator is the base for testing any possible modifications that may be included into the DVB-T2 future standard. In fact, several proposed enhancements have already been carried out and their performance has been evaluated. Specifically, the use of higher order modulation schemes, and the corresponding modifications in all the system blocks, have been included and evaluated. Furthermore, the simulator will allow testing other enhancements as the use of more efficient encoders and interleavers, MIMO technologies, and so on. A complete set of numerical results showing the performance of the different parts of the system, are presented in order to validate the correctness of the implementation and to evaluate both the current standard performance and the proposed enhancements. This work has been performed within the context of a project called FURIA, which is a strategic research project funded by the Spanish Ministry of Industry, Tourism and Commerce. A brief description of this project and its consortium has been also included herein, together with an introduction to the current situation of the DTTB in Spain (called TDT in Spanish)

A Differential Turbo Detection Aided Sphere Packing Modulated Space-Time Coding Scheme

A signal construction method that combines orthogonal design with sphere packing has recently shown useful performance improvements over the conventional orthogonal design. In this contribution, we extend this concept and propose a novel Sphere Packing (SP) modulated differential Space-Time Block Coded (DSTBC) scheme, referred to here as (DSTBC-SP), which shows performance advantages over conventional DSTBC schemes. We also demonstrate that the performance of DSTBC-SP systems can be further improved by concatenating sphere packing aided modulation with channel coding and performing SP-symbol-to bit demapping as well as channel decoding iteratively. We also investigate the convergence behaviour of this concatenated scheme with the aid of Extrinsic Information Transfer (EXIT) Charts. The proposed turbo-detected DSTBC-SP scheme exhibits a ’turbo-cliff’ at Eb/N0 = 6dB and provides Eb/N0 gains of 23.7dB and 1.7dB at a BER of 10?5 over an equivalent-throughput uncoded DSTBC-SP scheme and a turbo-detected QPSK modulated DSTBC scheme, respectively

EQUALISATION TECHNIQUES FOR MULTI-LEVEL DIGITAL MAGNETIC RECORDING

A large amount of research has been put into areas of signal processing, medium design, head and servo-mechanism design and coding for conventional longitudinal as well as perpendicular magnetic recording. This work presents some further investigation in the signal processing and coding aspects of longitudinal and perpendicular digital magnetic recording. The work presented in this thesis is based upon numerical analysis using various simulation methods. The environment used for implementation of simulation models is C/C + + programming. Important results based upon bit error rate calculations have been documented in this thesis. This work presents the new designed Asymmetric Decoder (AD) which is modified to take into account the jitter noise and shows that it has better performance than classical BCJR decoders with the use of Error Correction Codes (ECC). In this work, a new method of designing Generalised Partial Response (GPR) target and its equaliser has been discussed and implemented which is based on maximising the ratio of the minimum squared euclidean distance of the PR target to the noise penalty introduced by the Partial Response (PR) filter. The results show that the new designed GPR targets have consistently better performance in comparison to various GPR targets previously published. Two methods of equalisation including the industry's standard PR, and a novel Soft-Feedback- Equalisation (SFE) have been discussed which are complimentary to each other. The work on SFE, which is a novelty of this work, was derived from the problem of Inter Symbol Interference (ISI) and noise colouration in PR equalisation. This work also shows that multi-level SFE with MAP/BCJR feedback based magnetic recording with ECC has similar performance when compared to high density binary PR based magnetic recording with ECC, thus documenting the benefits of multi-level magnetic recording. It has been shown that 4-level PR based magnetic recording with ECC at half the density of binary PR based magnetic recording has similar performance and higher packing density by a factor of 2. A novel technique of combining SFE and PR equalisation to achieve best ISI cancellation in a iterative fashion has been discussed. A consistent gain of 0.5 dB and more is achieved when this technique is investigated with application of Maximum Transition Run (MTR) codes. As the length of the PR target in PR equalisation increases, the gain achieved using this novel technique consistently increases and reaches up to 1.2 dB in case of EEPR4 target for a bit error rate of 10-5

Error-Correction Coding and Decoding: Bounds, Codes, Decoders, Analysis and Applications

Coding; Communications; Engineering; Networks; Information Theory; Algorithm

Near-capacity fixed-rate and rateless channel code constructions

Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder

On performance analysis and implementation issues of iterative decoding for graph based codes

There is no doubt that long random-like code has the potential to achieve good performance because of its excellent distance spectrum. However, these codes remain useless in practical applications due to the lack of decoders rendering good performance at an acceptable complexity. The invention of turbo code marks a milestone progress in channel coding theory in that it achieves near Shannon limit performance by using an elegant iterative decoding algorithm. This great success stimulated intensive research oil long compound codes sharing the same decoding mechanism. Among these long codes are low-density parity-check (LDPC) code and product code, which render brilliant performance. In this work, iterative decoding algorithms for LDPC code and product code are studied in the context of belief propagation. A large part of this work concerns LDPC code. First the concept of iterative decoding capacity is established in the context of density evolution. Two simulation-based methods approximating decoding capacity are applied to LDPC code. Their effectiveness is evaluated. A suboptimal iterative decoder, Max-Log-MAP algorithm, is also investigated. It has been intensively studied in turbo code but seems to be neglected in LDPC code. The specific density evolution procedure for Max-Log-MAP decoding is developed. The performance of LDPC code with infinite block length is well-predicted using density evolution procedure. Two implementation issues on iterative decoding of LDPC code are studied. One is the design of a quantized decoder. The other is the influence of mismatched signal-to-noise ratio (SNR) level on decoding performance. The theoretical capacities of the quantized LDPC decoder, under Log-MAP and Max-Log-MAP algorithms, are derived through discretized density evolution. It is indicated that the key point in designing a quantized decoder is to pick a proper dynamic range. Quantization loss in terms of bit error rate (BER) performance could be kept remarkably low, provided that the dynamic range is chosen wisely. The decoding capacity under fixed SNR offset is obtained. The robustness of LDPC code with practical length is evaluated through simulations. It is found that the amount of SNR offset that can be tolerated depends on the code length. The remaining part of this dissertation deals with iterative decoding of product code. Two issues on iterative decoding of\u27 product code are investigated. One is, \u27improving BER performance by mitigating cycle effects. The other is, parallel decoding structure, which is conceptually better than serial decoding and yields lower decoding latency

Bit-Wise Decoders for Coded Modulation and Broadcast Coded Slotted ALOHA

This thesis deals with two aspects of wireless communications. The first aspect is about efficient point-to-point data transmission. To achieve high spectral efficiency, coded modulation, which is a concatenation of higher order modulation with error correction coding, is used. Bit-interleaved coded modulation (BICM) is a pragmatic approach to coded modulation, where soft information on encoded bits is calculated at the receiver and passed to a bit-wise decoder. Soft information is usually obtained in the form of log-likelihood ratios (also known as L-values), calculated using the max-log approximation. In this thesis, we analyze bit-wise decoders for pulse-amplitude modulation (PAM) constellations over the additive white Gaussian noise (AWGN) channel when the max-log approximation is used for calculating L-values. First, we analyze BICM systems from an information theoretic perspective. We prove that the max-log approximation causes information loss for all PAM constellations and labelings with the exception of a symmetric 4-PAM constellation labeled with a Gray code. We then analyze how the max-log approximation affects the generalized mutual information (GMI), which is an achievable rate for a standard BICM decoder. Second, we compare the performance of the standard BICM decoder with that of the ML decoder. We show that, when the signal-to-noise ratio (SNR) goes to infinity, the loss in terms of pairwise error probability is bounded by 1.25 dB for any two codewords. The analysis further shows that the loss is zero for a wide range of linear codes. The second aspect of wireless communications treated in this thesis is multiple channel access. Our main objective here is to provide reliable message exchange between nodes in a wireless ad hoc network with stringent delay constraints. To that end, we propose an uncoordinated medium access control protocol, termed all-to-all broadcast coded slotted ALOHA (B-CSA), that exploits coding over packets at the transmitter side and successive interference cancellation at the receiver side. The protocol resembles low-density parity-check codes and can be analyzed using the theory of codes on graphs. The packet loss rate performance of the protocol exhibits a threshold behavior with distinct error floor and waterfall regions. We derive a tight error floor approximation that is used for the optimization of the protocol. We also show how the error floor approximation can be used to design protocols for networks, where users have different reliability requirements. We use B-CSA in vehicular networks and show that it outperforms carrier sense multiple access currently adopted as the MAC protocol for vehicular communications. Finally, we investigate the possibility of establishing a handshake in vehicular networks by means of B-CSA