Electricity from photovoltaic solar cells: Flat-Plate Solar Array Project final Report. Volume III: Silicon sheet: wafers and ribbons

The Flat-Plate Solar Array (FSA) Project, funded by the U.S. Government and managed by the Jet Propulsion Laboratory, was formed in 1975 to develop the module/array technology needed to attain widespread terrestrial use of photovoltaics by 1985. To accomplish this, the FSA Project established and managed an Industry, University, and Federal Government Team to perform the needed research and development. The primary objective of the Silicon Sheet Task of the FSA Project was the development of one or more low-cost technologies for producing silicon sheet suitable for processing into cost-eompetitive solar cells. Silicon sheet refers to high-purity crystalline silicon of size and thickness for fabrication into solar cells. The Task effort began with state-of-the-art sheet technologies and then solicited and supported any new silicon sheet alternatives that had the potential to achieve the Project goals. A total of 48 contracts were awarded that covered work in the areas of ingot growth and casting, wafering, ribbon growth, other sheet technologies, and programs of supportive research. Periodic reviews of each sheet technology were held, assessing the technical progress and the long-range potential. Technologies that failed to achieve their promise, or seemed to have lower probabilities for success in comparison with others, were dropped. A series of workshops was initiated to assess the state of the art, to provide insights into problems remaining to be addressed, and to support technology transfer. The Task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high-quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the Task cost goals were not achieved. This FSA Final Report (JPL Publication 86-31, 5101-289, DOE/JPL 1012-125, October 1986) is composed of eight volumes, consisting of an Executive Summary and seven technology reports: Volume I: Executive Summary. Volume II: Silicon Material. Volume III: Silicon Sheet: Wafers and Ribbons Volume IV: High-Efficiency Solar Celis. Volume V: Process Development. Volume VI: Engineering Sciences and Reliability. Volume VII: Module Encapsulation. Volume VIII: Project Analysis and Integration. Two supplemental reports included in the final report package are: FSA Project: 10 Years of Progress, JPL Document 400-279. 5101-279, October 1985. Summary of FSA Project Documentation: Abstracts of Published Documents, 1975 to 1986, JPL Publication 82-79 (Revision 1),5101-221, DOE/JPL-1 012-76, September 1986

Photovoltaic technologies

Photovoltaics is already a billion dollar industry. It is experiencing rapid growth as concerns over fuel supplies and carbon emissions mean that governments and individuals are increasingly prepared to ignore its current high costs. It will become truly mainstream when its costs are comparable to other energy sources. At the moment, it is around four times too expensive for competitive commercial production. Three generations of photovoltaics have been envisaged that will take solar power into the mainstream. Currently, photovoltaic production is 90% first-generation and is based on silicon wafers. These devices are reliable and durable, but half of the cost is the silicon wafer and efficiencies are limited to around 20%. A second generation of solar cells would use cheap semiconductor thin films deposited on low-cost substrates to produce devices of slightly lower efficiency. A number of thin-film device technologies account for around 5–6% of the current market. As second-generation technology reduces the cost of active material, the substrate will eventually be the cost limit and higher efficiency will be needed to maintain the cost-reduction trend. Third-generation devices will use new technologies to produce high-efficiency devices. Advances in nanotechnology, photonics, optical metamaterials, plasmonics and semiconducting polymer sciences offer the prospect of cost-competitive photovoltaics. It is reasonable to expect that cost reductions, a move to second-generation technologies and the implementation of new technologies and third-generation concepts can lead to fully cost- competitive solar energy in 10–15 years

High and low threshold P-channel metal oxide semiconductor process and description of microelectronics facility

The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs

Nanowire Zinc Oxide MOSFET Pressure Sensor

Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology

Wet chemical etching mechanism of silicon

We review what can be said on wet chemical etching of single crystals from the viewpoint of the science of crystal growth. Starting point is that there are smooth and rough crystal surfaces. The kinetics of smooth faces is controlled by a nucleation barrier that is absent on rough faces. The latter therefore etch faster by orders of magnitude. The analysis of the diamond crystal structure reveals that the {111} face is the only smooth face in this lattice-other faces might be smooth only because of surface reconstruction. In this way we explain the minimum of the etch rate in KOH:H2O in the <001> direction. Two critical predictions concerning the shape of the minimum of the etch rate close to <001> and the transition from isotropic to anisotropic etching in HF:HNO3 based solutions are tested experimentally. The results are in-agreement with the theor

Energy requirement for the production of silicon solar arrays

Photovoltaics is subject of an extensive technology assessment in terms of its net energy potential as an alternate energy source. Reduction of quartzite pebbles, refinement, crystal growth, cell processing and panel building are evaluated for energy expenditure compared to direct, indirect, and overhead energies

Hybrid integration methods for on-chip quantum photonics

The goal of integrated quantum photonics is to combine components for the generation, manipulation, and detection of nonclassical light in a phase-stable and efficient platform. Solid-state quantum emitters have recently reached outstanding performance as single-photon sources. In parallel, photonic integrated circuits have been advanced to the point that thousands of components can be controlled on a chip with high efficiency and phase stability. Consequently, researchers are now beginning to combine these leading quantum emitters and photonic integrated circuit platforms to realize the best properties of each technology. In this paper, we review recent advances in integrated quantum photonics based on such hybrid systems. Although hybrid integration solves many limitations of individual platforms, it also introduces new challenges that arise from interfacing different materials. We review various issues in solid-state quantum emitters and photonic integrated circuits, the hybrid integration techniques that bridge these two systems, and methods for chip-based manipulation of photons and emitters. Finally, we discuss the remaining challenges and future prospects of on-chip quantum photonics with integrated quantum emitters. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreemen

Energy requirement for the production of silicon solar arrays

An assessment of potential changes and alternative technologies which could impact the photovoltaic manufacturing process is presented. Topics discussed include: a multiple wire saw, ribbon growth techniques, silicon casting, and a computer model for a large-scale solar power plant. Emphasis is placed on reducing the energy demands of the manufacturing process