Perturbation of the sierpinski antenna to allocate the operating bands

A scheme for modifying the spacing between the bands of the Sierpinski antenna is introduced. Experimental results of two novel designs of fractal antennas suggest that the fractal structure can be perturbed to enable the log-period to be changed while still maintaining the multiband behaviour of the antenna.Peer ReviewedPostprint (published version

Study of spin-scan imaging for outer planets missions

The constraints that are imposed on the Outer Planet Missions (OPM) imager design are of critical importance. Imager system modeling analyses define important parameters and systematic means for trade-offs applied to specific Jupiter orbiter missions. Possible image sequence plans for Jupiter missions are discussed in detail. Considered is a series of orbits that allow repeated near encounters with three of the Jovian satellites. The data handling involved in the image processing is discussed, and it is shown that only minimal processing is required for the majority of images for a Jupiter orbiter mission

E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods

During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post-silicon validation are mostly manual and ad hoc, and, hence, extremely expensive and time consuming. This is particularly true for subtle electrical bugs caused by unexpected interactions between a design and its electrical state. We present E-QED, a new approach that automatically localizes electrical bugs during post-silicon validation. Our results on the OpenSPARC T2, an open-source 500-million-transistor multicore chip design, demonstrate the effectiveness and practicality of E-QED: starting with a failed post-silicon test, in a few hours (9 hours on average) we can automatically narrow the location of the bug to (the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on average for a design with ~ 1 Million flip-flops) and also obtain the corresponding bug trace. The area impact of E-QED is ~2.5%. In contrast, deter-mining this same information might take weeks (or even months) of mostly manual work using traditional approaches

Design of On-Chip Self-Testing Signature Register

Over the last few years, scan test has turn out to be too expensive to implement for industry standard designs due to increasing test data volume and test time. The test cost of a chip is mainly governed by the resource utilization of Automatic Test Equipment (ATE). Also, it directly depends upon test time that includes time required to load test program, to apply test vectors and to analyze generated test response of the chip. An issue of test time and data volume is increasingly appealing designers to use on-chip test data compactors, either on input side or output side or both. Such techniques significantly address the former issues but have little hold over increasing number of input-outputs under test mode. Further, test pins on DUT are increasing over the generations. Thus, scan channels on test floor are falling short in number for placement of such ICs. To address issues discussed above, we introduce an on-chip self-testing signature register. It comprises a response compactor and a comparator. The compactor compacts large chunk of response data to a small test signature whereas the comparator compares this test signature with desired one. The overall test result for the design is generated on single output pin. Being no storage of test response is demanded, the considerable reduction in ATE memory can be observed. Also, with only single pin to be monitored for test result, the number of tester channels and compare edges on ATE side significantly reduce at the end of the test. This cuts down maintenance and usage cost of test floor and increases its life time. Furthermore reduction in test pins gives scope for DFT engineers to increase number of scan chains so as to further reduce test time

Dynamic input match correction in R.F. low noise amplifiers

An R.F. circuit that recognizes its faults, and then corrects its performance in real-time has been the holy-grail of RFIC design. This work presents, for the first time, a complete architecture and successful implementation of such a circuit. It is the first step towards the grand vision of fault-free, package independent, integrated R.F. Front End circuitry. The performance of R.F. front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input. These inductances have wide tolerances and are difficult to co-design for. A novel methodology, which overcomes current obstacles plaguing such an objective, is proposed wherein the affected performance metric of the circuit is quantified, and the appropriate design parameter is modified in real-time, thus enabling self-correction. This proof of concept is demonstrated by designing a cascode LNA and the complete self-correction circuit in IBM 0.25 µm CMOS RF process. The self-correction circuitry ascertains the input match frequency of the circuit by measuring its performance and determines the frequency interval by which it needs to be shifted to restore it to the desired value. It then feeds back a digital word to the LNA which adaptively corrects its input-match. It offers the additional flexibility of using different packages for the front-end since it renders the circuitry independent of package parasitics, by re-calibrating the input match on-the-fly. The circuitry presented in this work offers the advantages of low power, robustness, absence of DSP cores or processors, reduction in design cycle times, guaranteed optimal performance under varying conditions and fast correction times (less than 30 µs)

Design de circuitos RFID multi-ressonantes sem chip como substitutos dos códigos de barras

The chipless RFID technology , appears from an e ort to design low-cost RFID tags without the use of traditional silicone Application Specific Integrated Circuits (ASICs) that are the price bottleneck of the typicall RFID technology. In this way, tags become fully passive and without any active processing unit, thus the Chipless RFID system have more similarities with the Radio Detection And Ranging (RADAR) systems than with the common RFID systems. This dissertation sheds light on the problems and challenges that the RFID technology has as replacement of the optical barcode labels, discuss the state of the art of the chipless RFID technology and presents a model to describe the relationship between the multi-resonant circuit resonant frequency and the resonant spirals length. Finally, a chipless RFID system is simulated making use of the fractional Fourier Transform as means to separate linear frequency modulated signals that collide in both time and frequency domain. The results achieved with dissertation not only aid designers with the synthesis of multi-resonant circuits but also prove the reliability of the use of the fractional Fourier Transform as a means of manipulating the time-frequency domain and successfully recovering individual tags' ID from a signal containing more than one collided backscattered signal.A tecnologia de RFID sem chip, surgiu de um esforço para obter etiquetas RFID de baixo custo sem o uso de circuitos integrados de aplicação especifica (ASICs) que são a restrição à diminuição dos preço dos tipicos sistemas RFID. Desta forma, as tags tornam-se totalmente passivas e sem nenhuma unidade de processamento ativa, passando, os sistemas RFID sem chip a ter mais semelhanças com os sistemas de Radio Detection And Ranging (RADAR) do que com os sistemas RFID comuns. Esta dissertação esclarece os problemas e desafios que a tecnologia RFID enfrenta enquanto substituta das etiquetas de código de barras apresentando também o estado da arte da tecnologia RFID sem chip. Também apresenta e propõe um modelo para descrever a relação entre a frequência de ressonância do circuito multi-ressonante e o comprimento das espirais ressonantes. Finalmente, um sistema RFID sem chip é simulado usando a transformada fracionária de Fourier como meio de separar sinais modulados linearmente em frequência que colidem simultaneamente no domínio do tempo e da frequência. Os resultados alcançados com esta dissertação por um lado ajudam os projetistas com a síntese de circuitos multi-ressonantes e por outro provam a confiabilidade do uso da transformada fracionária de Fourier como um meio de manipular o domínio tempo-frequência para recuperar com sucesso informa ção individual de ID a partir de um sinal que contém mais de um sinal transmistido de uma etiqueta sem chip.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Secure Split Test for Preventing IC Piracy by Un-Trusted Foundry and Assembly

In the era of globalization, integrated circuit design and manufacturing is spread across different continents. This has posed several hardware intrinsic security issues. The issues are related to overproduction of chips without knowledge of designer or OEM, insertion of hardware Trojans at design and fabrication phase, faulty chips getting into markets from test centers, etc. In this thesis work, we have addressed the problem of counterfeit IC‟s getting into the market through test centers. The problem of counterfeit IC has different dimensions. Each problem related to counterfeiting has different solutions. Overbuilding of chips at overseas foundry can be addressed using passive or active metering. The solution to avoid faulty chips getting into open markets from overseas test centers is secure split test (SST). The further improvement to SST is also proposed by other researchers and is known as Connecticut Secure Split Test (CSST). In this work, we focus on improvements to CSST techniques in terms of security, test time and area. In this direction, we have designed all the required sub-blocks required for CSST architecture, namely, RSA, TRNG, Scrambler block, study of benchmark circuits like S38417, adding scan chains to benchmarks is done. Further, as a security measure, we add, XOR gate at the output of the scan chains to obfuscate the signal coming out of the scan chains. Further, we have improved the security of the design by using the PUF circuit instead of TRNG and avoid the use of the memory circuits. This use of PUF not only eliminates the use of memory circuits, but also it provides the way for functional testing also. We have carried out the hamming distance analysis for introduced security measure and results show that security design is reasonably good.Further, as a future work we can focus on: • Developing the circuit which is secuered for the whole semiconductor supply chain with reasonable hamming distance and less area overhead

Fault-tolerant design of RF front-end circuits

The continuing trends of scaling in the CMOS industry have, inevitably, been accompanied by an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Two main reasons have contributed to the fact that fault-tolerant solutions for circuits that operate in the GHz domain have not been realized so far. First, GHz signals are extremely sensitive to higher-order effects such as stray pick-ups, interference, package & on-chip parasitics, etc. Secondly, the use of passives, especially inductors, in the feedback path poses huge area overheads, in addition to a slew of instability problems due to wide variations and soft faults. Hence traditional fault-tolerance methods used in digital and low frequency analog circuits cannot be applied in the RF domain. This work presents a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique is minimally intrusive and is transparent during \u27normal\u27 use of the circuit. It is characterized by low area and power overheads, does not need any off-chip computing or DSP cores, and is characterized by self-correction times in the range of a few hundreds of microseconds. It compares very well with existing commercial RF test solutions that use DSP cores and require hundreds of milliseconds. The methodology is demonstrated on a LNA, since it is critical for the performance of the entire front-end. It is validated with simulation and fabrication results of the system designed in IBM 0.25 µm CMOS 6RF process