Digital signal processing: the impact of convergence on education, society and design flow

Design and development of real-time, memory and processor hungry digital signal processing systems has for decades been accomplished on general-purpose microprocessors. Increasing needs for high-performance DSP systems made these microprocessors unattractive for such implementations. Various attempts to improve the performance of these systems resulted in the use of dedicated digital signal processing devices like DSP processors and the former heavyweight champion of electronics design – Application Specific Integrated Circuits. The advent of RAM-based Field Programmable Gate Arrays has changed the DSP design flow. Software algorithmic designers can now take their DSP algorithms right from inception to hardware implementation, thanks to the increasing availability of software/hardware design flow or hardware/software co-design. This has led to a demand in the industry for graduates with good skills in both Electrical Engineering and Computer Science. This paper evaluates the impact of technology on DSP-based designs, hardware design languages, and how graduate/undergraduate courses have changed to suit this transition

Internationalisation of Innovation: Why Chip Design Moving to Asia

This paper will appear in International Journal of Innovation Management, special issue in honor of Keith Pavitt, (Peter Augsdoerfer, Jonathan Sapsed, and James Utterback, guest editors), forthcoming. Among Keith Pavitt's many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge But chip design, a process that creates the greatest value in the electronics industry and that requires highly complex knowledge, is experiencing a massive dispersion to leading Asian electronics exporting countries. To explain why chip design is moving to Asia, the paper draws on interviews with 60 companies and 15 research institutions that are doing leading-edge chip design in Asia. I demonstrate that "pull" and "policy" factors explain what attracts design to particular locations. But to get to the root causes that shift the balance in favor of geographical decentralization, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design") and organization ("vertical specialization" within global design networks). The resultant increase in knowledge mobility explains why chip design - that, in Pavitt's framework is not supposed to move - is moving from the traditional centers to a few new specialized design clusters in Asia. A completely revised and updated version has been published as: " Complexity and Internationalisation of Innovation: Why is Chip Design Moving to Asia?," in International Journal of Innovation Management, special issue in honour of Keith Pavitt, Vol. 9,1: 47-73.

Working on a Start-Up: A Case for An Applied Entrepreneurship Oriented Course for Senior Undergraduates

In this paper, we describe a new teaching approach whose objective is to implement entrepreneurship-based learning. The proposed teaching approach is essentially a project-based approach, but, with two novel key components that give it the entrepreneurship emphasis. First, the main idea is to divide students into groups of four or five members and have each team go through the process of starting-up a company. This process tries to emulate all steps through which entrepreneurs go when a new start-up idea is taken from concept to product realization. These steps include proposing a novel start-up idea, writing a business plan, coming up with a solution, implementing and testing the solution, and reporting results. The only constraint of this “exercise” is that all start-up ideas must be related to the main topic of the course, which in our case is that of advanced hardware description language and field-programmable gate array (FPGA) digital design. As a second component, each student is required to maintain a so called individual reflective journal (IRJ). Students add new entries of about half a page each week to the IRJ, which plays the role of a diary. The objective of this component is to engage students in thinking about how the course activities tie into the three components of the KEEN framework: curiosity, connections, and creation of value. The projected outcomes of this teaching approach include: 1) help students to develop an entrepreneurial mindset, 2) foster creativity and self-learning, and 3) engage students more and enable them to be proactive and competition-aware

TechNews digests: Jan - Mar 2010

TechNews is a technology, news and analysis service aimed at anyone in the education sector keen to stay informed about technology developments, trends and issues. TechNews focuses on emerging technologies and other technology news. TechNews service : digests september 2004 till May 2010 Analysis pieces and News combined publish every 2 to 3 month

How Sustainable are Benefits from Global Production Networks? Malaysia's Upgrading Prospects in the Electronics Industry

The paper introduces an operational definition of industrial upgrading (IU and documents the emergence of complex, multi-tier "networks of networks" which provide new opportunities for IU, but which also raise threshold requirements for participating in these networks. I highlight structural weaknesses of the Malaysian electronics industry that constrain its upgrading prospects; assess current policies that try to link cluster development and global network integration; discuss adjustments in linkages with global brand leaders (OEMs); and ask to what degree linkages with contract manufacturers (CMs) can broaden network benefits. The paper concludes, by exploring new opportunities for international knowledge sourcing that could complement Malaysia's linkages with GPNs. A completely revised and updated version has been published as: "Global Production Networks and Industrial Upgrading -Malaysia's Electronics Industry", in: J. Kidd and F.J. Richter, eds., Trust and Anti-Trust in Cross-Cultural Alliances, published for the World Economic Forum, Palgrave, London, 2003.

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation