Establishing an electrical test philosophy for LSI microcircuits, volume 2 Final report, 15 May 1970 - 15 Feb. 1971

Large scale integration microelectronic wafer and package testing including parametric and functional tests of combinatorial and sequential logic circuit

Fault detection in asynchronous sequential circuits

As the asynchronous sequential circuit has become more and more important to digital systems in recent years high reliability and simple maintenance of the circuit is stressed. This paper presents a fault-detection algorithm which will be applicable to most of the practical asynchronous sequential circuits. The asynchronous sequential circuit is treated from the combinatoric point of view. First the minimal set of states, both stable states and unstable states, sufficient to detect all possible faults of the circuit is found from the fault table. Then a test sequence is generated to go through these states. It is assumed that testing outputs can be added. Simple and systematic techniques are also presented for the construction of fault table and the generation of test sequence. The usefulness of this algorithm increases as the density of the stable states associated with the circuit increases --Abstract, page ii

Scan cell design for enhanced delay fault testability

Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cel

Alternative methods of steady-state testing sequential digital logic integrated circuits

The steady-state testing of a sequential digital integrated circuit requires control the logic states of the internal bistable flip-flops

Genetic algorithm as self-test path and circular self-test path design method

The paper presents the use of Genetic Algorithm to search for non-linear Autonomous Test Structures (ATS) in Built-In Testing approach. Such structures can include essentially STP and CSTP and their modifications. Non-linear structures are more difficult to analyze than the widely used structures such as independent Test Pattern Generator and the Test Response Compactor realized by Linear Feedback Shift Registers. To reduce time-consuming test simulation of sequential circuit, it was used an approach based on the stochastic model of pseudo-random testing. The use of stochastic model significantly affects the time effectiveness of the search for evolutionary autonomous structures. In test simulation procedure, the block of sequential circuit memory is not disconnected. This approach does not require a special selection of memory registers such as BILBOs. A series of studies to test circuits set ISCAS’89 are made. The results of the study are very promising

Dual enhancement mechanisms for overnight motor memory consolidation

Our brains are constantly processing past events<sup>1</sup>. These offline processes consolidate memories, leading in the case of motor skill memories to an enhancement in performance between training sessions. A similar magnitude of enhancement develops over a night of sleep following an implicit task, in which a sequence of movements is acquired unintentionally, or following an explicit task, in which the same sequence is acquired intentionally<sup>2</sup>. What remains poorly understood, however, is whether these similar offline improvements are supported by similar circuits, or through distinct circuits. We set out to distinguish between these possibilities by applying transcranial magnetic stimulation over the primary motor cortex (M1) or the inferior parietal lobule (IPL) immediately after learning in either the explicit or implicit task. These brain areas have both been implicated in encoding aspects of a motor sequence and subsequently supporting offline improvements over sleep<sup>3,​4,​5</sup>. Here we show that offline improvements following the explicit task are dependent on a circuit that includes M1 but not IPL. In contrast, offline improvements following the implicit task are dependent on a circuit that includes IPL but not M1. Our work establishes the critical contribution made by M1 and IPL circuits to offline memory processing, and reveals that distinct circuits support similar offline improvements

Gate Delay Fault Test Generation for Non-Scan Circuits

This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation-backward justification technique: The test pattern generation is started at the fault location, and after successful ¿local¿ test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this pape