Overcoming a Communication Barrier on the Way Towards a Global Sensor Network

In a global sensor network different sensor platforms will be deployed. A grave obstacle on the way of building sensor networks out of different sensor nodes are incompatible implementations of network protocol stacks used with different sensor node platforms. We describe our efforts to overcome this obstacle in a heterogeneous sensor network consisting out of MICAz Motes and Sun SPOTs, both using an IEEE 802.15.4 radio chip. We explain the major differences in the respective network stacks and our approach to bridge them. A network stack that bridges the gap between different platforms allows for more flexible and robust networks

A Communication Monitor for Wireless Sensor Networks Based on Software Defined Radio

Link quality estimation of reliability-crucial wireless sensor networks (WSNs) is often limited by the observability and testability of single-chip radio transceivers. The estimation is often based on collection of packer-level statistics, including packet reception rate, or vendor-specific registers, such as CC2420's Received Signal Strength Indicator (RSSI) and Link Quality Indicator (LQI). The speed or accuracy of such metrics limits the performance of reliability mechanisms built in wireless sensor networks. To improve link quality estimation in WSNs, we designed a powerful wireless communication monitor based on Software Defined Radio (SDR). We studied the relations between three implemented link quality metrics and packet reception rate under different channel conditions. Based on a comparison of the metrics' relative advantages, we proposed using a combination of them for fast and accurate estimation of a sensor network link

An interface chip for saw based sensor in an ad-hoc network

The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to ad hoc network architecture remains a challenge. This work involves the design of an interface chip for a Surface Acoustic Wave (SAW) based chemical sensor where the sensor reflects the RF input and introduces a time delay proportional to the concentration of the vapors absorbed by it. The interface chip detects the frequency shift as a function of the chemical species absorbed by the sensor and alerts the ad hoc network controller when a monitored parameter exceeded some threshold, based on local processing and measurements. System components are designed in an RF environment to carry out the local processing and estimation of the chemical absorbed. Simulation results for individual circuit components as well as the complete chip outline the robust performance of the system that improves chemical target detection and reduce false alarms. The design takes into account a sensor system with ten chemical SAW sensors operating at a resonant frequency of 1 GHz and an attenuation of 30 dB. The circuit is designed in to produce an alarm signal for a frequency shift of 1kHz due to a change in chemical concentration at the sensor, in 0.35 µ technology. The performance of the chip can be improved by scaling the design to 0.18 µ technology

Thermal profiling of homogeneous multi-core processors using sensor mini-networks

With large-scale integration and high power density in current generation microprocessors, thermal management is becoming a critical component of system design. Specifically, accurate thermal monitoring using on-die sensors is vital for system reliability and recovery. Achieving an accurate thermal profile of a system with an optimal number of sensors is integral for thermal management. This work focuses on a sensor placement mechanism and an on-chip sensor mini-network to combine temperatures from multiple sensors to determine the full thermal profile of a chip. The sensor placement mechanism proposed in this work uses non-uniform subsampling of thermal maps with k-means clustering. Using this sensing technique with cubic interpolation, an 8-core architecture thermal map was successfully recovered with an average error improvement of 90% over sensor placement via basic k-means clustering. All the simulations were run using HotSpot 5.0 modeling Alpha 21364 processor as a baseline core. The sensor mini-network using both differential encoding and distributed source coding was analyzed on a 1024-core architecture. Distributed source coding compression required fewer transmissions than differential encoding and reduced the number of transmitted bits by 36% over a sensor mini-network with no compression

An ANT-based Sensor Measurement Data Gathering System

Large-scale industries involved with a great amount of sensor measurements in their work are facing many challenges in data collection. Sensors are not on the same network; therefore each measurement has to be managed separately. Gathering all the measurement data to one terminal could be difficult. Once a measurement is obtained, it takes significant amount of time to process the data.The approaches our group takes here is to build a giant ANT wireless network that holds all the sensors’ measurements. To be more specific, every sensor has an ANT chip set up on its side. Each ANT chip is as a single node. And on PC terminal, there is also a ANT chip which is collecting data from all the nodes. Microsoft Visual C++ and Keil uVision are used to program the program on PC and the program on ANT chip, respectively. Sending a “start measurement operation code” from ANT USB stick on PC terminal to the embedded ANT board starts the measurement. During the development, acknowledged data transfer type was found to be most effective, out of three data transfer types: broadcast, burst, acknowledged. This generalized solution can be easily applied to all kinds of sensor application

A sensor-less NBTI mitigation methodology for NoC architectures

CMOS technology improvement allows to increase the number of cores integrated on a single chip and makes Network-on-Chips (NoCs) a key component from the performance and reliability standpoints. Unfortunately, continuous scaling of CMOS technology poses severe concerns regarding failure mechanisms such as NBTI and stressmigration, that are crucial in achieving acceptable component lifetime. Process variation complicates the scenario, decreasing device lifetime and performance predictability during chip fabrication. This paper presents a novel sensor-less methodology to reduce the NBTI degradation in the on-chip network virtual channel buffers, considering process variation effects as well. Experimental validation is obtained using a cycle accurate simulator considering both real and synthetic traffic patterns. We compare our methodology to the best sensor-wise approach used as reference golden model. The proposed sensor-less strategy achieves results within 25% to the optimal sensor-wise methodology while this gap is reduced around 10% decreasing the number of virtual channels per input port. Moreover, our proposal can mitigate NBTI impact both in short and long run, since we recover both the most degraded VC (short run) as well as all the other VCs (long term)

An embedded sensor node microcontroller with crypto-processors

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed

Design Of Neural Network Circuit Inside High Speed Camera Using Analog CMOS 0.35 ¼m Technology

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs , readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network