Parsing a sequence of qubits

We develop a theoretical framework for frame synchronization, also known as block synchronization, in the quantum domain which makes it possible to attach classical and quantum metadata to quantum information over a noisy channel even when the information source and sink are frame-wise asynchronous. This eliminates the need of frame synchronization at the hardware level and allows for parsing qubit sequences during quantum information processing. Our framework exploits binary constant-weight codes that are self-synchronizing. Possible applications may include asynchronous quantum communication such as a self-synchronizing quantum network where one can hop into the channel at any time, catch the next coming quantum information with a label indicating the sender, and reply by routing her quantum information with control qubits for quantum switches all without assuming prior frame synchronization between users.Comment: 11 pages, 2 figures, 1 table. Final accepted version for publication in the IEEE Transactions on Information Theor

High-rate self-synchronizing codes

Self-synchronization under the presence of additive noise can be achieved by allocating a certain number of bits of each codeword as markers for synchronization. Difference systems of sets are combinatorial designs which specify the positions of synchronization markers in codewords in such a way that the resulting error-tolerant self-synchronizing codes may be realized as cosets of linear codes. Ideally, difference systems of sets should sacrifice as few bits as possible for a given code length, alphabet size, and error-tolerance capability. However, it seems difficult to attain optimality with respect to known bounds when the noise level is relatively low. In fact, the majority of known optimal difference systems of sets are for exceptionally noisy channels, requiring a substantial amount of bits for synchronization. To address this problem, we present constructions for difference systems of sets that allow for higher information rates while sacrificing optimality to only a small extent. Our constructions utilize optimal difference systems of sets as ingredients and, when applied carefully, generate asymptotically optimal ones with higher information rates. We also give direct constructions for optimal difference systems of sets with high information rates and error-tolerance that generate binary and ternary self-synchronizing codes.Comment: 9 pages, no figure, 2 tables. Final accepted version for publication in the IEEE Transactions on Information Theory. Material presented in part at the International Symposium on Information Theory and its Applications, Honolulu, HI USA, October 201

Codes for protection from synchronization loss and additive errors

Codes for protection from synchronization loss and additive error

Command system study for the operation and control of unmanned scientific satellites. task ii closed-loop /feedback/ verification techniques second quarterly progress report, 30 sep. - 31 dec. 1964

Closed loop, feedback verification techniques for command system of unmanned scientific satellit

A study of high density bit transition requirements versus the effects on BCH error correcting coding

Several methods for increasing bit transition densities in a data stream are summarized, discussed in detail, and compared against constraints imposed by the 2 MHz data link of the space shuttle high rate multiplexer unit. These methods include use of alternate pulse code modulation waveforms, data stream modification by insertion, alternate bit inversion, differential encoding, error encoding, and use of bit scramblers. The psuedo-random cover sequence generator was chosen for application to the 2 MHz data link of the space shuttle high rate multiplexer unit. This method is fully analyzed and a design implementation proposed

A study of high density bit transition requirements versus the effects on BCH error correcting codes

The use of PN sequence generators to create a minimum number of transitions in an NRZ bit stream is described. The CSG encoder/decoder design was constructed and demonstrated

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast