Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Design techniques for low-power SAR ADCs in nano-scale CMOS technologies

This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Electrical and Computer Engineerin

Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies

This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.Electrical and Computer Engineerin

Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step

An 8-Bit Analog-to-Digital Converter for Battery Operated Wireless Sensor Nodes

Wireless sensing networks (WSNs) collect analog information transduced into the form of a voltage or current. This data is typically converted into a digital representation of the value and transmitted wirelessly using various modulation techniques. As the available power and size is limited for wireless sensor nodes in many applications, a medium resolution Analog-to-Digital Converter (ADC) is proposed to convert a sensed voltage with moderate speeds to lower power consumption. Specifications also include a rail-to-rail input range and minimized errors associated with offset, gain, differential nonlinearity, and integral nonlinearity. To achieve these specifications, an 8-bit successive approximation register ADC is developed which has a conversion time of nine clock cycles. This ADC features a charge scaling array included to achieve minimized power consumption and area by reducing unit capacitance in the digital-to-analog converter. Furthermore, a latched comparator provides fast decisions utilizing positive feedback. The ADC was designed and simulated using Cadence Virtuoso with parasitic extraction over expected operating temperature range of 0 – 85°C. The design was fabricated using TSMC’s 65 nanometer RF GP process and tested on a printed circuit board to verify design specifications. The measured results for the device show an offset and gain error of +7 LSB and 31.1 LSB, respectively, and a DNL range of -0.9 LSB to +0.8 LSB and an INL range of approximately -4.6 LSB to +12 LSB. The INL is much improved in regard to the application of the temperature sensor. The INL for this region of interest is from -3.5 LSB to +2.8 LSB

A 12-bit SAR ADC for a flexible tactile sensor

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) are some of the most efficient ADC topologies available, allowing excellent performance values at low power consumption across a wide range of sampling frequencies. The proposed ADC is aimed at a tactile sensor application, requiring a low-noise and lowpower solution. In addition, it should have high SNDR to detect even the weakest signals with precision. This thesis presents a 12-bit 400 kS/s SAR ADC implemented in a 180 nm CMOS technology for such a task. The designed SAR ADC uses a hybrid R-C DAC topology consisting of a chargescaling MSB DAC and a voltage-scaling LSB DAC, allowing a good trade-off between power consumption, layout area and performance while keeping the total DAC capacitance under reasonable values. Bootstrapped switches have been implemented to preserve high-linearity during the sampling period. A double-tail dynamic comparator has been designed to obtain a low-noise measurement while ensuring suitable delay values. Finally, regarding the logic, an asynchronous implementation and the conventional switching algorithm provide a simple but effective solution to supply the digital signals of the design. Pre-layout noise simulations with input frequencies around 200 kHz show SNDR values of 72.07 dB, corresponding to an ENOB of 11.67 bits. The total power consumption is 365 ?W while the Walden and Schreier figure-of-merit (FoM) correspond to values of 275 fJ/conversion and 160 dB, respectively

Low-power high-performance SAR ADC with redundancy and digital background calibration

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 195-199).As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm² with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB₁₂ INL and +0.5/-0.7 LSB₁₂ DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.by Albert Hsu Ting Chang.Ph.D