Secure Intermittent-Robust Computation For Energy Harvesting Device Security And Outage Resilience

In this paper, we propose Secure Intermittent-Robust Computation (SIRC) for Energy Harvesting Powered Internet of Things (IoT) Devices. This effort innovates a new duty-cycle-variable computing approach to facilitate and invigorate security in energy-harvesting-powered IoT network nodes. The proposed SIRC architecture is developed from the ground up by extending emerging post-CMOS switching elements to realize majority-gate logic that is intrinsically-capable of middleware-coherent, battery-free without check-pointing or micro-Tasking, and can be resilient to wireless power transfer attacks including charge attacks and data attacks. Potential countermeasures for these attacks are identified at the circuit-level through gate-resolution immunity of power interruption. As a proof-of-concept, a power-maskable design using SIRC approach is developed for s27 circuit from ISCAS89 benchmark. The obtained results shows SIRC provides reduced area consumption and increase number of power traces to extract crypted data

Normally-Off Computing Design Methodology Using Spintronics: From Devices to Architectures

Energy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle-variable computing approach leveraging the non-volatility inherent in post-CMOS switching devices. The foundations of EIC will be advanced from the ground up by extending Spin Hall Effect Magnetic Tunnel Junction (SHE-MTJ) device models to realize SHE-MTJ-based Majority Gate (MG) and Polymorphic Gate (PG) logic approaches and libraries, that leverage intrinsic-non-volatility to realize middleware-coherent, intermittent computation without checkpointing, micro-tasking, or software bloat and energy overheads vital to IoT. Device-level EIC research concentrates on encapsulating SHE-MTJ behavior with a compact model to leverage the non-volatility of the device for intrinsic provision of intermittent computation and lifetime energy reduction. Based on this model, the circuit-level EIC contributions will entail the design, simulation, and analysis of PG-based spintronic logic which is adaptable at the gate-level to support variable duty cycle execution that is robust to brief and extended supply outages or unscheduled dropouts, and development of spin-based research synthesis and optimization routines compatible with existing commercial toolchains. These tools will be employed to design a hybrid post-CMOS processing unit utilizing pipelining and power-gating through state-holding properties within the datapath itself, thus eliminating checkpointing and data transfer operations