Study of Single-Event Transient Effects on Analog Circuits

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment. Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects. The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance

Total Dose Simulation for High Reliability Electronics

abstract: New technologies enable the exploration of space, high-fidelity defense systems, lighting fast intercontinental communication systems as well as medical technologies that extend and improve patient lives. The basis for these technologies is high reliability electronics devised to meet stringent design goals and to operate consistently for many years deployed in the field. An on-going concern for engineers is the consequences of ionizing radiation exposure, specifically total dose effects. For many of the different applications, there is a likelihood of exposure to radiation, which can result in device degradation and potentially failure. While the total dose effects and the resulting degradation are a well-studied field and methodologies to help mitigate degradation have been developed, there is still a need for simulation techniques to help designers understand total dose effects within their design. To that end, the work presented here details simulation techniques to analyze as well as predict the total dose response of a circuit. In this dissertation the total dose effects are broken into two sub-categories, intra-device and inter-device effects in CMOS technology. Intra-device effects degrade the performance of both n-channel and p-channel transistors, while inter-device effects result in loss of device isolation. In this work, multiple case studies are presented for which total dose degradation is of concern. Through the simulation techniques, the individual device and circuit responses are modeled post-irradiation. The use of these simulation techniques by circuit designers allow predictive simulation of total dose effects, allowing focused design changes to be implemented to increase radiation tolerance of high reliability electronics.Dissertation/ThesisPh.D. Electrical Engineering 201

Ionizing radiation e\ufb00ects in nanoscale CMOS technologies exposed to ultra-high doses

This thesis studies the e\ufb00ects of radiation in nanoscale CMOS technologies exposed to ultra-high total ionizing doses (TID), up to 1 Grad(SiO2). These extreme radiation levels are orders of magnitude higher that those typically experienced by space applications (where radiation e\ufb00ects in electronic are of concern). However, they can be found in some speci\ufb01c applications like the large-hadron-collider (LHC) of CERN, and, in particular, in its future upgrade, the high-luminosity LHC (HL-LHC). The study at such high doses has both revealed new phenomena, and has contributed to a better understanding of some of the already known radiation-induced e\ufb00ects. The radiation response of four di\ufb00erent CMOS technology nodes, i.e., 130, 65, 40 and 28 nm, coming from di\ufb00erent manufacturers, has been investigated in di\ufb00erent conditions of temperature, bias, dose-rate and for di\ufb00erent transistor\u2019s sizes, providing an unique and comprehensive set of data about the ultra-high TID-induced phenomena in modern CMOS technologies. This study has con\ufb01rmed that the thin gate oxide of nanoscale technologies is extremely robust to radiation, even at ultra-high doses. The main cause of performance degradation has been identi\ufb01ed in the presence of auxiliary oxides such as shallow trench insulation oxides (STI) and spacers. Both radiation-induced drain-to-source leakage current increase and radiation-induced narrow channel e\ufb00ect (RINCE) are caused by positive charge trapped in the STI. In this work, thanks to exposures to very high TID levels and to measurements performed in di\ufb00erent conditions of temperature and bias, we show that the two e\ufb00ects are provoked by charge trapped in di\ufb00erent locations along the trench oxide. Moreover, a new unexpected ultra-high-dose drain current increase (UCLI) e\ufb00ect, a\ufb00ecting narrow and long nMOS transistors, has been observed. In-depth studies of the radiation-induced short channel e\ufb00ect (RISCE), related to the presence of the spacers, have shown that, at ultra-high doses, the degradation mechanism consists of two phases. A \ufb01rst increase of the series resistance, caused by the radiation-induced charge trapping in the spacers, is followed by a threshold voltage shift provoked by the transport of hydrogen ions from the spacers to the gate oxide. This model has been validated by several static measurements, TCAD simulations and charge pumping measurements. The dependencies of these e\ufb00ects on bias, temperature and size of the transistors have also been studied in detail. Moreover, an unexpected true dose-rate sensitivity has been measured in both nMOS and pMOS transistors in 65 and 130 nm technologies, although the radiation response of MOS devices is considered insensitive to true dose-rate e\ufb00ects. The current degradation in samples irradiated at a dose-rate comparable to that expected in the HL-LHC is larger by a factor of 3c2 than that measured in the typical quali\ufb01cation test, usually carried out with a much higher dose-rate. This is clearly of serious concern for the quali\ufb01cation of circuits designed for the particle detectors of the HL-LHC

Combined Effects of Radio Frequency and Electron Radiation on CMOS Inverters

This research examines the measurement methodology, and the results of, the combined effects of electron and radio frequency irradiation (500kHz) on a CMOS Hex Inverter, CD4069UB. There have been many studies in recent years on the effects of electron radiation and electromagnetic interference on integrated circuits, however the combined effects have not been measured. A major obstacle for in-situ electron irradiation experiments is the over current hazard that exists to measurement equipment that comes from taking real-time, in-situ measurements. To overcome this, a test circuit was designed and built to allow for real-time in-situ measurement of the output voltage, current and the inverter power. This test circuit provides real–time measurement of the inverter’s threshold voltage with respect to electron dose. During this research pre- and post-electron irradiation measurements (1MeVelectrons with fluences up to 8x1015[e-/cm-2] at various fluxes), combined with RF were made using a continuous 500kHz RF signal coupled into the inverter input. The data provided insight into the total dose effect as opposed to a dose rate effect on the inverter. A significant negative threshold voltage shift was observed along with a limited amount of annealing. Inverters that were outliners from nominal VTC characteristics displayed an enhanced failure rate. The combined effects of radio frequency are inconclusive, but indicate that the RF decreases post irradiation annealing

Capacitance-Voltage Study on the Effects of Low Energy Electron Radiation on Al\u3ci\u3e\u3csub\u3e0.27\u3c/i\u3e\u3c/sub\u3eGa\u3ci\u3e\u3csub\u3e0.73\u3c/i\u3e\u3c/sub\u3eN/GaN High Electron Mobility Transistor

The effects of radiation on semiconductors are extremely important to the Department of Defense since the majority of the defense informational, navigational and communications systems are now satellite-based. Due to the high radiation tolerance of gallium nitride and a plethora of high temperature, high power and high frequency applications, the prospect that gallium nitride based devices will become key components in a multitude of military satellite-based systems is highly probable. AlGaN/GaN HEMTs were irradiated at low temperature (~80 K) by 0.45 – 0.8 MeV electrons up to fluences of 1×1015 e-/cm2. Following irradiation, low temperature capacitance-voltage measurements were recorded providing fluence-dependent measurements; additionally low-temperature post-irradiation capacitance-voltage measurements were recorded at twenty-four hour intervals up to 72 hours in order to investigate the room temperature annealing process. Using previously irradiated devices, the effects of a 9 month and 12 month room temperature anneal were also considered. Capacitance-voltage measurements indicate that low energy electron radiation results in an increase in the transistor channel drain current. These increases occur both at low and room temperature. The mechanism, clearly shown through capacitance-voltage measurements, causing the increase in drain current is an increase in the carrier concentration in the 2DEG. This result is due to donor electrons from a nitrogen vacancy in the gallium nitride. The devices begin to anneal immediately and show almost complete recovery after 72 hours

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications

The instrumentation of radiation detectors for high energy physics calls for the development of very low-noise application-specific integrated-circuits and demanding system-level design strategies, with a particular focus on the minimisation of inter-ference noise from power anagement circuitry. On the other hand, the aggressive pixelisation of sensors and associated front-end electronics, and the high radiation exposure at the innermost tracking and vertex detectors, requires radiation-aware design and radiation-tolerant deep sub-micron CMOS technologies. This thesis explores circuit design techniques towards radiation tolerant power management integrated circuits, targeting applications on particle detectors and monitoring of accelerator-based experiments, aerospace and nuclear applications. It addresses advantages and caveats of commonly used radiation-hard layout techniques, which often employ Enclosed Layout or H-shaped transistors, in respect to the use of linear transistors. Radiation tolerant designs for bandgap circuits are discussed, and two different topologies were explored. A low quiescent current bandgap for sub-1 V CMOS circuits is proposed, where the use of diode-connected MOSFETs in weak-inversion is explored in order to increase its radiation tolerance. An any-load stable LDO architecture is proposed, and three versions of the design using different layout techniques were implemented and characterised. In addition, a switched DC-DC Buck converter is also studied. For reasons concerning testability and silicon area, the controller of the Buck converter is on-chip, while the inductance and the power transistors are left on-board. A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. The chip features Linear, ELT and H-shape LDO designs, bandgap circuits and a Buck DC-DC converter. We discuss the design, layout and test results of the prototype. The specifications in terms of voltage range and output current capability are based on the requirements set for the integrated on-detector electronics of the new CGEM-IT tracker for the BESIII detector. The thesis discusses the fundamental aspects of the proposed on-detector electronics and provides an in-depth depiction of the front-end design for the readout ASIC

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V