Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures

There is an ever-increasing demand for energy efficiency (EE) in rapidly evolving Internet-of-Things end nodes. This pushes researchers and engineers to develop solutions that provide both Application-Specific Integrated Circuit-like EE and Field-Programmable Gate Array-like flexibility. One such solution is Coarse Grain Reconfigurable Array (CGRA). Over the past decades, CGRAs have evolved and are competing to become mainstream hardware accelerators, especially for accelerating Digital Signal Processing (DSP) applications. Due to the over-specialization of computing architectures, the focus is shifting towards fitting an extensive data representation range into fewer bits, e.g., a 32-bit space can represent a more extensive data range with floating-point (FP) representation than an integer representation. Computation using FP representation requires numerous encodings and leads to complex circuits for the FP operators, decreasing the EE of the entire system. This thesis presents the design of an EE ultra-low-power CGRA with native support for FP computation by leveraging an emerging paradigm of approximate computing called transprecision computing. We also present the contributions in the compilation toolchain and system-level integration of CGRA in a System-on-Chip, to envision the proposed CGRA as an EE hardware accelerator. Finally, an extensive set of experiments using real-world algorithms employed in near-sensor processing applications are performed, and results are compared with state-of-the-art (SoA) architectures. It is empirically shown that our proposed CGRA provides better results w.r.t. SoA architectures in terms of power, performance, and area

Effective interprocess communication (IPC) in a real-time transputer network

The thesis describes the design and implementation of an interprocess communication (IPC) mechanism within a real-time distributed operating system kernel (RT-DOS) which is designed for a transputer-based network. The requirements of real-time operating systems are examined and existing design and implementation strategies are described. Particular attention is paid to one of the object-oriented techniques although it is concluded that these techniques are not feasible for the chosen implementation platform. Studies of a number of existing operating systems are reported. The choices for various aspects of operating system design and their influence on the IPC mechanism to be used are elucidated. The actual design choices are related to the real-time requirements and the implementation that has been adopted is described. [Continues.

Protocolo de comunicações sem-fios em malha para redes de iluminação pública

Mestrado em Engenharia Eletrónica e TelecomunicaçõesThe digital revolution of the 21st century contributed to stem the Internet of Things (IoT). Trillions of embedded devices using the Internet Protocol (IP), also called smart objects, will be an integral part of the Internet. In order to support such an extremely large address space, a new Internet Protocol, called Internet Protocol Version 6 (IPv6) is being adopted. The IPv6 over Low Power Wireless Personal Area Networks (6LoWPAN) has accelerated the integration of WSNs into the Internet. At the same time, the Constrained Application Protocol (CoAP) has made it possible to provide resource constrained devices with RESTful Web services functionalities. This work builds upon previous experience in street lighting networks, for which a proprietary protocol, devised by the Lighting Living Lab, was implemented and used for several years. The proprietary protocol runs on a broad range of lighting control boards. In order to support heterogeneous applications with more demanding communication requirements and to improve the application development process, it was decided to port the Contiki OS to the four channel LED driver (4LD) board from Globaltronic. This thesis describes the work done to adapt the Contiki OS to support the Microchip TM PIC24FJ128GA308 microprocessor and presents an IP based solution to integrate sensors and actuators in smart lighting applications. Besides detailing the system’s architecture and implementation, this thesis presents multiple results showing that the performance of CoAP based resource retrievals in constrained nodes is adequate for supporting networking services in street lighting networks.A revolução digital do século 21 contribuiu para o surgimento da Internet das Coisas (IoT). Em breve triliões de dispositivos embutidos usando o Internet Protocol (IP) serão parte integrante da Internet. De modo a suportar tal gama de endereços, um novo protocolo de Internet, chamado Internet Protocol versão 6 (IPv6) está a ser adoptado. O IPv6 over Low power Wireless Personal Area Networks (6LoWPAN) acelerou a integração das redes sem-fios de sensores na Internet. Ao mesmo tempo, o Constrained Application Protocol (CoAP) tornou possível fornecer funcionalidades de serviços Web RESTful a dispositivos com recursos limitados. Este trabalho baseia-se em experiências anteriores em redes de iluminação pública, para os quais um protocolo proprietário, elaborado pelo Lighting Living Lab, foi implementado e usado durante vários anos. O protocolo proprietário tem sido utilizado numa ampla gama de placas de controlo de iluminação. De modo a suportar aplicações heterogéneas com requisitos de comunicação mais exigentes além de melhorar o processo de desenvolvimento de aplicações, adaptou-se o Contiki OS à placa LED driver de 4 canais (4LD) da Globaltronic. Esta dissertação descreve o trabalho conduzido para adaptar o Contiki OS ao microprocessador Microchip TM PIC24FJ128GA308 e apresenta uma solução baseada em IP para integrar sensores e atuadores em aplicações de iluminação inteligentes. Além da descrição da arquitetura e da implementação do sistema, este trabalho apresenta vários resultados que mostram que o desempenho do protocolo CoAP na placa 4LD é adequado para suportar serviços Web em redes de iluminação pública

Real-time systems on multicore platforms: managing hardware resources for predictable execution

Shared hardware resources in commodity multicore processors are subject to contention from co-running threads. The resultant interference can lead to highly-variable performance for individual applications. This is particularly problematic for real-time applications, which require predictable timing guarantees. It also leads to a pessimistic estimate of the Worst Case Execution Time (WCET) for every real-time application. More CPU time needs to be reserved, thus less applications can enter the system. As the average execution time is usually far less than the WCET, a significant amount of reserved CPU resource would be wasted. Previous works have attempted partitioning the shared resources, amongst either CPUs or processes, to improve performance isolation. However, they have not proven to be both efficient and effective. In this thesis, we propose several mechanisms and frameworks that manage the shared caches and memory buses on multicore platforms. Firstly, we introduce a multicore real-time scheduling framework with the foreground/background scheduling model. Combining real-time load balancing with background scheduling, CPU utilization is greatly improved. Besides, a memory bus management mechanism is implemented on top of the background scheduling, making sure bus contention is under control while utilizing unused CPU cycles. Also, cache partitioning is thoroughly studied in this thesis, with a cache-aware load balancing algorithm and a dynamic cache partitioning framework proposed. Lastly, we describe a system architecture to integrate the above solutions all together. It tackles one of the toughest problems in OS innovation, legacy support, by converting existing OSes into libraries in a virtualized environment. Thus, within a single multicore platform, we benefit from the fine-grained resource control of a real-time OS and the richness of functionality of a general-purpose OS

The 1989 Goddard Conference on Space Applications of Artificial Intelligence

The following topics are addressed: mission operations support; planning and scheduling; fault isolation/diagnosis; image processing and machine vision; data management; and modeling and simulation

1992 NASA/ASEE Summer Faculty Fellowship Program

For the 28th consecutive year, a NASA/ASEE Summer Faculty Fellowship Program was conducted at the Marshall Space Flight Center (MSFC). The program was conducted by the University of Alabama and MSFC during the period June 1, 1992 through August 7, 1992. Operated under the auspices of the American Society for Engineering Education, the MSFC program, was well as those at other centers, was sponsored by the Office of Educational Affairs, NASA Headquarters, Washington, DC. The basic objectives of the programs, which are the 29th year of operation nationally, are (1) to further the professional knowledge of qualified engineering and science faculty members; (2) to stimulate and exchange ideas between participants and NASA; (3) to enrich and refresh the research and teaching activities of the participants' institutions; and (4) to contribute to the research objectives of the NASA centers

Design of a modular digital computer system

A design tradeoff study is reported for a modular spaceborne computer system that is responsive to many mission types and phases. The computer uses redundancy to maximize reliability, and multiprocessing to maximize processing capacity. Fault detection and recovery features provide optimal reliability

Scalable and interference aware wi-fi mesh networks using cots devices

A crescente tendencia no acesso móvel tem sido potenciada pela tecnologia IEEE 802.11. Contudo, estas redes têm alcance rádio limitado. Para a extensão da sua cobertura é possível recorrer a redes emalhadas sem fios baseadas na tecnologia IEEE 802.11, com vantagem do ponto de vista do custo e da flexibilidade de instalação, face a soluções cabladas. Redes emalhadas sem fios constituídas por nós com apenas uma interface têm escalabilidade reduzida. A principal razão dessa limitação deve-se ao uso do mecanismo de acesso ao meio partilhado Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) em topologias multi-hop. Especificamente, o CSMA/CA não evita o problema do nó escondido levando ao aumento do número de colisões e correspondente degradação de desempenho com impacto direto no throughput e na latência. Com a redução da tecnologia rádio torna-se viável a utilização de múltiplos rádios por nó, sem com isso aumentar significativamente o custo da solução final de comunicações. A utilização de mais do que um rádio por nó de comuniações permite superar os problemas de desempenho inerentes ás redes formadas por nós com apenas um rádio. O objetivo desta tese, passa por desenvolver uma nova solução para redes emalhadas multi-cana, duar-radio, utilizando para isso novos mecanismos que complementam os mecanismos definidos no IEEE 802.11 para o estabelecimento de um Basic Service Set (BSS). A solução é baseada na solução WiFIX, um protocolo de routing para redes emalhadas de interface única e reutiliza os mecanismos já implementados nas redes IEEE 802.11 para difundir métricas que permitam à rede escalar de forma eficaz minimizando o impacto na performance. A rede multi-hop é formada por nós equipados com duas interfaces, organizados numa topologia hierárquica sobre múltiplas relações Access Point (AP) – Station (STA). Os resultados experimentais obtidos mostram a eficácia e o bom desempenho da solução proposta face à solução WiFIX original.The increasing trend on mobile access has been mainly potentied for IEEE 802.11 technology. However these networks suffer from reduced radio range. The extension of coverage can be potentiated by mesh deployments since they provide an ease, robust, flexible and cost effective solution for this problem. These networks are built upon nodes scattered in a mesh topology that form the backbone of an extended basic service set. Single radio Wireless Mesh Networks (WMN) however suffer from reduced scalability. The main reason to such limitation is the use of Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) in the multi-hop topology. Specifically, CSMA/CA fails to prevent the hidden and exposed node occurrence, which respectively, lead to an increase on the number of collisions and flow retentions. The direct impact on throughput and latency reduces the overall network performance to values that no longer match user increasing demands. As radio technology becomes cheaper, it became possible to equip nodes with multiple interfaces and operate them in multiple channels in order the reduce interference from links operating on a common channel. Therefore the goal of this thesis is to develop a new WMN Multi-Radio Multi-Channel (MRMC) solution addressing new mechanisms not yet covered in state of art. The proposed solution, is based on WiFIX, a Single Radio (SR) WMN routing protocol and reuses the mechanisms already implemented in IEEE 802.11 networks to broadcast metrics that enable the network to auto-configure efficiently and to scale with minimum overhead. The multi-hop backbone is formed by nodes equipped with two interfaces disposed in a hierarchical topology, under multiple Access Point (AP) - Station (STA) relations. The results obtained from an experimental testbed clearly show the effectiveness of the solution compared with the original WiFIX and its capability to scale resulting from the overhead control and co-channel interference reduction