Sensing and Regulation from Nucleic Acid Devices

abstract: The highly predictable structural and thermodynamic behavior of deoxynucleic acid (DNA) and ribonucleic acid (RNA) have made them versatile tools for creating artificial nanostructures over broad range. Moreover, DNA and RNA are able to interact with biological ligand as either synthetic aptamers or natural components, conferring direct biological functions to the nucleic acid devices. The applications of nucleic acids greatly relies on the bio-reactivity and specificity when applied to highly complexed biological systems. This dissertation aims to 1) develop new strategy to identify high affinity nucleic acid aptamers against biological ligand; and 2) explore highly orthogonal RNA riboregulators in vivo for constructing multi-input gene circuits with NOT logic. With the aid of a DNA nanoscaffold, pairs of hetero-bivalent aptamers for human alpha thrombin were identified with ultra-high binding affinity in femtomolar range with displaying potent biological modulations for the enzyme activity. The newly identified bivalent aptamers enriched the aptamer tool box for future therapeutic applications in hemostasis, and also the strategy can be potentially developed for other target molecules. Secondly, by employing a three-way junction structure in the riboregulator structure through de-novo design, we identified a family of high-performance RNA-sensing translational repressors that down-regulates gene translation in response to cognate RNAs with remarkable dynamic range and orthogonality. Harnessing the 3WJ repressors as modular parts, we integrate them into biological circuits that execute universal NAND and NOR logic with up to four independent RNA inputs in Escherichia coli.Dissertation/ThesisDoctoral Dissertation Biochemistry 201

A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler

Hierarchical temporal memory (HTM) is a biomimetic machine learning algorithm focused upon modeling the structural and algorithmic properties of the neocortex. It is comprised of two components, realizing pattern recognition of spatial and temporal data, respectively. HTM research has gained momentum in recent years, leading to both hardware and software exploration of its algorithmic formulation. Previous work on HTM has centered on addressing performance concerns; however, the memory-bound operation of HTM presents significant challenges to scalability. In this work, a scalable flash-based storage processor unit, Flash-HTM (FHTM), is presented along with a detailed analysis of its potential scalability. FHTM leverages SSD flash technology to implement the HTM cortical learning algorithm spatial pooler. The ability for FHTM to scale with increasing model complexity is addressed with respect to design footprint, memory organization, and power efficiency. Additionally, a mathematical model of the hardware is evaluated against the MNIST dataset, yielding 91.98% classification accuracy. A fully custom layout is developed to validate the design in a TSMC 180nm process. The area and power footprints of the spatial pooler are 30.538mm2 and 5.171mW, respectively. Storage processor units have the potential to be viable platforms to support implementations of HTM at scale

New Approaches for Memristive Logic Computations

Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore\u27s Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new emerging technologies such as memristors. Memristors are non-volatile and nanoscale devices and can be used for building memory arrays with very high density (extending Moore\u27s law). Memristors can also be used to perform stateful logic operations where the same devices are used for logic and memory, enabling in-memory logic. In other words, memristor-based stateful logic enables a new computing paradigm of combining calculation and memory units (versus von Neumann architecture of separating calculation and memory units). This reduces the delays between processor and memory by eliminating redundant reloading of reusable values. In addition, memristors consume low power hence can decrease the large amounts of power dissipation in silicon chips hitting their size limit. The primary focus of this research is to develop the circuit implementations for logic computations based on memristors. These implementations significantly improve the performance and decrease the power of digital circuits. This dissertation demonstrates in-memory computing using novel memristive logic gates, which we call volistors (voltage-resistor gates). Volistors capitalize on rectifying memristors, i.e., a type of memristors with diode-like behavior, and use voltage at input and resistance at output. In addition, programmable diode gates, i.e., another type of logic gates implemented with rectifying memristors are proposed. In programmable diode gates, memristors are used only as switches (unlike volistor gates which utilize both memory and switching characteristics of the memristors). The programmable diode gates can be used with CMOS gates to increase the logic density. As an example, a circuit implementation for calculating logic functions in generalized ESOP (Exclusive-OR-Sum-of-Products) form and multilevel XOR network are described. As opposed to the stateful logic gates, a combination of both proposed logic styles decreases the power and improves the performance of digital circuits realizing two-level logic functions Sum-of-Products or Product-of-Sums. This dissertation also proposes a general 3-dimentional circuit architecture for in-memory computing. This circuit consists of a number of stacked crossbar arrays which all can simultaneously be used for logic computing. These arrays communicate through CMOS peripheral circuits

A review on continuous-flow microfluidic PCR in droplets : advances, challenges and future

Significant advances have been made in developing microfluidic polymerase chain reaction (PCR) devices in the last two decades. More recently, microfluidic microdroplet technology has been exploited to perform PCR in droplets because of its unique features. For example, it can prevent crossover contamination and PCR inhibition, is suitable for single-cell and single molecule analyses, and has the potential for system integration and automation. This review will therefore focus on recent developments on droplet-based continuous-flow microfluidic PCR, and the major research challenges. This paper will also discuss a new way of on-chip flow control and a rational design simulation tool, which are required to underpin fully integrated and automated droplet-based microfluidic systems. We will conclude with a scientific speculation of future autonomous scientific discoveries enabled by microfluidic microdroplet technologies

Programming microbes to treat superbug infection

Superbug infection is one of the greatest public health threat with grave implications across all levels of society. Towards a new solution to combat infection by multi-drug resistant bacteria, this thesis presents an engineering framework and genetic tools applied to repurpose commensal bacteria into “micro-robots” for the treatment of superbug infection. Specifically, a prototype of designer probiotic was developed using the human commensal bacteria Escherichia coli. The engineered commensal was reprogrammed with user-specified functions to sense superbug, produced pathogen-specific killing molecules and released the killing molecules via a lytic mechanism. The engineered commensal was effective in suppressing ~99% of planktonic Pseudomonas and preventing ~ 90% of biofilm formation. To enhance the sensing capabilities of engineered commensal, genetic interfaces comprising orthogonal AND & OR logic devices were developed to mediate the integration and interpretation of binary input signals. Finally, AND, OR and NOT logic gates were networked to generate a myriad of cellular logic operations including half adder and half subtractor. The creation of half adder logic represents a significant advancement of engineering human commensal to be biological equivalent of microprocessor chips in programmable computer with the ability to process input signals into diversified actions. Importantly, this thesis provides exemplary case studies to the attenuation of cellular and genetic context dependent effects through principles elucidated herein, thereby advancing our capability to engineer commensal bacteria.Open Acces

In-Memory Computing by Using Nano-ionic Memristive Devices

By reaching to the CMOS scaling limitation based on the Moore’s law and due to the increasing disparity between the processing units and memory performance, the quest is continued to find a suitable alternative to replace the conventional technology. The recently discovered two terminal element, memristor, is believed to be one of the most promising candidates for future very large scale integrated systems. This thesis is comprised of two main parts, (Part I) modeling the memristor devices, and (Part II) memristive computing. The first part is presented in one chapter and the second part of the thesis contains five chapters. The basics and fundamentals regarding the memristor functionality and memristive computing are presented in the introduction chapter. A brief detail of these two main parts is as follows: Part I: Modeling- This part presents an accurate model based on the charge transport mechanisms for nanoionic memristor devices. The main current mechanism in metal/insulator/metal (MIM) structures are assessed, a physic-based model is proposed and a SPICE model is presented and tested for four different fabricated devices. An accuracy comparison is done for various models for Ag/TiO2/ITO fabricated device. Also, the functionality of the model is tested for various input signals. Part II: Memristive computing- Memristive computing is about utilizing memristor to perform computational tasks. This part of the thesis is divided into neuromorphic, analog and digital computing schemes with memristor devices. – Neuromorphic computing- Two chapters of this thesis are about biologicalinspired memristive neural networks using STDP-based learning mechanism. The memristive implementation of two well-known spiking neuron models, Hudgkin-Huxley and Morris-Lecar, are assessed and utilized in the proposed memristive network. The synaptic connections are also memristor devices in this design. Unsupervised pattern classification tasks are done to ensure the right functionality of the system. – Analog computing- Memristor has analog memory property as it can be programmed to different memristance values. A novel memristive analog adder is designed by Continuous Valued Number System (CVNS) scheme and its circuit is comprised of addition and modulo blocks. The proposed analog adder design is explained and its functionality is tested for various numbers. It is shown that the CVNS scheme is compatible with memristive design and the environment resolution can be adjusted by the memristance ratio of the memristor devices. – Digital computing- Two chapters are dedicated for digital computing. In the first one, a development over IMPLY-based logic with memristor is provided to implement a 4:2 compressor circuit. In the second chapter, A novel resistive over a novel mirrored memristive crossbar platform. Different logic gates are designed with the proposed memristive logic method and the simulations are provided with Cadence to prove the functionality of the logic. The logic implementation over a mirrored memristive crossbars is also assessed

An Ultra-Low-Power 75mV 64-Bit Current-Mode Majority-Function Adder

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions

Algorithm for Tant Synthesis and Its Sequential Application

Electrical Engineerin