A Survey on Layout Implementation and Analysis of Different SRAM Cell Topologies

Because powered widgets are frequently used, the primary goal of electronics is to design low-power devices. Because of its applications in low-energy computing, memory cell operation with low voltage consumption has become a major interest in memory cell design. Because of specification changes in scaled methodologies, the only critical method for the success of low-voltage SRAM design is the stable operation of SRAM. The traditional SRAM cell enables high-density and fast differential sensing but suffers from semi-selective and read-risk issues. The simulation results show that the proposed design provides the fastest read operation and overall power delay product optimization. Compared to the current topologies of 6T, 8T, and 10T, while a traditional SRAM cell solves the reading disruption problem, previous strategies for solving these problems have been ineffective due to low efficiency, data-dependent leakage, and high energy per connection. Our primary goal is to reduce power consumption, improve read performance, and reduce the area and power of the proposed design cell work. The proposed leakage reduction design circuit has been implemented on the micro-wind tool. Delay and power consumption are important factors in memory cell performance. The primary goal of this project is to create a low-power SRAM cell

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

The design of low-power SRAM cell becomes a necessity in today\u27s FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAM-based FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA

Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters

The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs\u27 increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells\u27 data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern. To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications. This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs\u27 threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process

Enhancing SRAM Cell Circuitry through PDLPDC Optimization

This study focuses on improving static random-access memory (SRAM) cell circuit design by leveraging the Power Dissipation Low Power Dissipation Circuit (PDLPDC). The PDLPDC, a low-power dissipation circuit, has gained widespread use in designing cells for read operations, write operations, and idle modes, contributing to power optimisation in submicron or nano-range Very Large Scale Integration (VLSI) designs. While various SRAM cells, including 6T and 10T configurations, have been developed, they often exhibit higher power consumption. In contrast, our PDLPDC-based approach operates at lower power levels. With the increasing integration of portable devices into everyday life, power optimisation has emerged as a critical challenge in modern VLSI technology. Many contemporary gadgets and systems rely on very Large-scale Integration (VLSI) technology, where static random-access memory (SRAM) blocks occupy substantial chip space and represent a significant source of leakage power in current systems. However, a common practice, scaling the supply voltage of SRAM macros can lead to elevated power dissipation. This research addresses the challenge by efficiently scaling the supply voltage of SRAM macros, resulting in an overall reduction in power dissipation. The study introduces 6T and 10T SRAM circuits that minimise power dissipation during read and write operations while maintaining reasonable performance and stability. The impact of process parameter variations on various design metrics, including read and write power, leakage power, leakage current, and latency, becomes a critical consideration in SRAM cell design with increased integration scale. The proposed circuit, optimised for the minimum power-delay product during read, write, and idle modes, is compared with traditional SRAM cells (6T and 10T) and demonstrates superior performance, reliability, and power efficiency. This research contributes to advancing the understanding of SRAM circuit design, especially in the context of power optimisation and process variations

Pareto Points in SRAM Design Using the Sleepy Stack Approach

Abstract. Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultra-low leakage SRAM design which we call "sleepy stack SRAM." Unlike the straightforward sleep approach, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6-T SRAM cell with high-Vth transistors, the sleepy stack SRAM cell with 2xVth at 110°C achieves, using 0.07µ technology models, more than 2.77X leakage power reduction at a cost of 16% delay increase and 113% area increase. Alternatively, by widening wordline transistors and transistors in the pull-down network, the sleepy stack SRAM cell can achieve 2.26X leakage reduction without increasing delay at a cost of a 125% area penalty

Memory Module Design for High-Temperature Applications in SiC CMOS Technology

The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is required to realize a complete electronic system in SiC that bridges the gap between data processing and data storage. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for future electronics. A novel static random-access memory (SRAM) cell is designed and implemented in a SiC 1 µm triple well CMOS process for high-temperature applications in this work. The prevalent issues encountered during SiC fabrication and the uncertainties in device performance led to 6T SRAM cell design modifications that enable adaptability to the worst and the best cases. However, design trade-offs are made in the design size, the number of transistors, number of I/Os, and the cell\u27s power consumption. The novel SRAM cell design mitigates the effect of poor p-type contacts after the device fabrication by controlling the cell\u27s drive strength via an additional pull-up network. The design also includes two parallel access transistors and separate wordlines that control both access transistors. This individual control enables post-fabrication tunability in the cell ratio (CR) and the pull-up (PR) ratio of the cell. It also allows tuning the access transistors\u27 effective width during a data read operation, and a data write operation, independently. Along with the SRAM cell design, the conventional latch-based sense amplifier is also designed in the SiC CMOS process to realize the monolithic memory IC modules. The SRAM cell performance is evaluated on the basis of static noise margin (SNM), write SNM (WSNM), read SNM (RSNM), leakage current, and read access time over a wide temperature range (25ºC to 500ºC) on three uniquely processed wafers. The noise margins measured on Wafer #2 show a lower leakage current of ~500 nA at 500ºC with the supply voltage of 10 V. The SNM of 6.07 V is measured at 500ºC with a 10 V of power supply. The read access time at 400ºC is ~7.5 µs at a supply voltage of 10 V

An Optimization of 16×16 SRAM Array for Low Power Applications

SRAM being Robust and having less read and write operation time is intended to use as a cache memory which oblige low power utilization. Low power SRAM outline is critical because it takes a vast division of aggregate power and pass on region in superior processors. A SRAM cell must meet the prerequisites for the operation in submicron/nano ranges. The scaling of CMOS innovation has critical effects on SRAM cell – arbitrary variance of electrical qualities and significant leakage current. The paper introduces the configuration of 16×16 SRAM array design including row decoders/drivers, column circuitry, sense amplifiers, pre charge circuitry and transmission gates utilizing Cadence tools in a unique way and its functionality is analyzed properly

Design and Analysis of Low-power SRAMs

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. Owing to high bitline voltage swing during write operation, the write power consumption is dominated the dynamic power consumption. The static power consumption is mainly due to the leakage current associated with the SRAM cells distributed in the array. Moreover, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent years. To reduce the write power consumption, several schemes such as row based sense amplifying cell (SAC) and hierarchical bitline sense amplification (HBLSA) have been proposed. However, these schemes impose architectural limitations on the design in terms of the number of words on a row. Beside, the effectiveness of these methods is limited to the dynamic power consumption. Conventionally, reduction of the cell supply voltage and exploiting the body effect has been suggested to reduce the cell leakage current. However, variation of the supply voltage of the cell associates with a higher dynamic power consumption and reduced cell data stability. Conventionally qualified by Static Noise Margin (SNM), the ability of the cell to retain the data is reduced under a lower supply voltage conditions. In this thesis, we revisit the concept of data stability from the dynamic perspective. A new criteria for the data stability of the SRAM cell is defined. The new criteria suggests that the access time and non-access time (recovery time) of the cell can influence the data stability in a SRAM cell. The speed vs. stability trade-off opens new opportunities for aggressive power reduction for low-power applications. Experimental results of a test chip implemented in a 130 nm CMOS technology confirmed the concept and opened a ground for introduction of a new operational mode for the SRAM cells. We introduced a new architecture; Segmented Virtual Grounding (SVGND) to reduce the dynamic and static power reduction in SRAM units at the same time. Thanks to the new concept for the data stability in SRAM cells, we introduced the new operational mode of Accessed Retention Mode (AR-Mode) to the SRAM cell. In this mode, the accessed SRAM cell can retain the data, however, it does not discharge the bitline. The new architecture outperforms the recently reported low-power schemes in terms of dynamic power consumption, thanks to the exclusive discharge of the bitline and the cell virtual ground. In addition, the architecture reduces the leakage current significantly since it uses the back body biasing in both load and drive transistors. A 40Kb SRAM unit based on SVGND architecture is implemented in a 130 nm CMOS technology. Experimental results exhibit a remarkable static and dynamic power reduction compared to the conventional and previously reported low-power schemes as expect from the simulation results