3D-MRI Obstruction and Visualization of Pharyngeal Airway Tract using Open Source Seeded Technique

Abstract: Obstructive Sleep Apnea(OSA) is breathing disorder syndrome in which the airway tract pauses during sleep due to collapse of pharyngeal airway. It is occurred at the sleep time, with fourth dimensional high resolution in airway tract Obstruction in children and adults with OSA. Here, we the operator places the seeds that includes the Oesopharyngeal air tract and found out a threshold for the first frame in order to determine the affected tissues which blocks the patients pharyngeal tract. In this automated segmentation method it shows the process of MRI studies of the pharyngeal air pathway and enable diagnose of obstructive tissues with the collapse tissues. Region growing method results well in Dice Coefficients compared with manual segmentation. It automatically detects 90% of collapse tissues. This approach leads to segment the pharyngeal pathway correctly. It uses long MRI scans in order to diagnosis the collapsed tissues with graph, accurate details and coefficients in a short span of duration

A Comprehensive Review of Distributed Coding Algorithms for Visual Sensor Network (VSN)

Since the invention of low cost camera, it has been widely incorporated into the sensor node in Wireless Sensor Network (WSN) to form the Visual Sensor Network (VSN). However, the use of camera is bringing with it a set of new challenges, because all the sensor nodes are powered by batteries. Hence, energy consumption is one of the most critical issues that have to be taken into consideration. In addition to this, the use of batteries has also limited the resources (memory, processor) that can be incorporated into the sensor node. The life time of a VSN decreases quickly as the image is transferred to the destination. One of the solutions to the aforementioned problem is to reduce the data to be transferred in the network by using image compression. In this paper, a comprehensive survey and analysis of distributed coding algorithms that can be used to encode images in VSN is provided. This also includes an overview of these algorithms, together with their advantages and deficiencies when implemented in VSN. These algorithms are then compared at the end to determine the algorithm that is more suitable for VSN

Cost-effective Hardware Design of a SPIHT Compression Algorithm

학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. Jae Ha Kim.Set Partitioning In Hierarchical Trees (SPIHT) is one of most popular embedded coding algorithms applied for wavelet coding images. It allows progressive transmission of information and gives high coding efficiency. In addition, it can omit entropy coding of the bit stream by arithmetic code with only small loss in performance. Thus it offers a cheaper and faster hardware design. In this dissertation, a cost-effective design of a SPIHT-based algorithm is proposed. In this algorithm, an image is partitioned into 1x64 blocks, each of which is transformed by DWT to generate wavelet coefficients. The wavelet coefficients are coded by SPIHT to generate bit-stream. Due to the mismatch of the data structure between DWT and SPIHT, the large buffers are required. In order to reduce buffers, a new data structure of wavelet coefficients and partitioned SPIHT are proposed. A wavelet-based block is partitioned into small sub-blocks each of which is compressed independently. To minimize distortion due to the sub-block-based compression, a bit-allocation scheme is proposed. The proposed design is implemented in both software and hardware. Experimental results show that the proposed design reduces the buffer size while minimizing the degradation of the rate-distortion performance. It is proved that the proposed design outperforms previous designs in hardware cost.Chapter Ⅰ. Introduction 1 Chapter Ⅱ. Basic Architecture of the compression algorithm 5 Chapter Ⅲ. A Partitioned NLS Algorithm 17 Chapter Ⅳ. Adjustment of the target bit lengths for individual sub-blocks Chapter Ⅴ. Experimental Results 35 Chapter Ⅵ. Conclusion 48 References 50 Abstract 52 초록 53Maste

Algorithms and Architectures for Secure Embedded Multimedia Systems

Embedded multimedia systems provide real-time video support for applications in entertainment (mobile phones, internet video websites), defense (video-surveillance and tracking) and public-domain (tele-medicine, remote and distant learning, traffic monitoring and management). With the widespread deployment of such real-time embedded systems, there has been an increasing concern over the security and authentication of concerned multimedia data. While several (software) algorithms and hardware architectures have been proposed in the research literature to support multimedia security, these fail to address embedded applications whose performance specifications have tighter constraints on computational power and available hardware resources. The goals of this dissertation research are two fold: 1. To develop novel algorithms for joint video compression and encryption. The proposed algorithms reduce the computational requirements of multimedia encryption algorithms. We propose an approach that uses the compression parameters instead of compressed bitstream for video encryption. 2. Hardware acceleration of proposed algorithms over reconfigurable computing platforms such as FPGA and over VLSI circuits. We use signal processing knowledge to make the algorithms suitable for hardware optimizations and try to reduce the critical path of circuits using hardware-specific optimizations. The proposed algorithms ensures a considerable level of security for low-power embedded systems such as portable video players and surveillance cameras. These schemes have zero or little compression losses and preserve the desired properties of compressed bitstream in encrypted bitstream to ensure secure and scalable transmission of videos over heterogeneous networks. They also support indexing, search and retrieval in secure multimedia digital libraries. This property is crucial not only for police and armed forces to retrieve information about a suspect from a large video database of surveillance feeds, but extremely helpful for data centers (such as those used by youtube, aol and metacafe) in reducing the computation cost in search and retrieval of desired videos

디스플레이 장치를 위한 고정 비율 압축 하드웨어 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 이혁재.디스플레이 장치에서의 압축 방식은 일반적인 비디오 압축 표준과는 다른 몇 가지 특징이 있다. 첫째, 특수한 어플리케이션을 목표로 한다. 둘째, 압축 이득, 소비 전력, 실시간 처리 등을 위해 하드웨어 크기가 작고, 목표로 하는 압축률이 낮다. 셋째, 래스터 주사 순서에 적합해야 한다. 넷째, 프레임 메모리 크기를 제한시키거나 임의 접근을 하기 위하여 압축 단위당 목표 압축률을 실시간으로 정확히 맞출 수 있어야 한다. 본 논문에서는 이와 같은 특징을 만족시키는 세 가지 압축 알고리즘과 하드웨어 구조를 제안하도록 한다. LCD 오버드라이브를 위한 압축 방식으로는 BTC(block truncation coding) 기반의 압축 방식을 제안하도록 한다. 본 논문은 압축 이득을 증가시키기 위하여 목표 압축률 12에 대한 압축 방식을 제안하는데, 압축 효율을 향상시키기 위하여 크게 두 가지 방법을 이용한다. 첫 번째는 이웃하는 블록과의 공간적 연관성을 이용하여 비트를 절약하는 방법이다. 그리고 두 번째는 단순한 영역은 2×16 코딩 블록, 복잡한 영역은 2×8 코딩 블록을 이용하는 방법이다. 2×8 코딩 블록을 이용하는 경우 목표 압축률을 맞추기 위하여 첫 번째 방법으로 절약된 비트를 이용한다. 저비용 근접-무손실 프레임 메모리 압축을 위한 방식으로는 1D SPIHT(set partitioning in hierarchical trees) 기반의 압축 방식을 제안하도록 한다. SPIHT은 고정 목표 압축률을 맞추는데 매우 효과적인 압축 방식이다. 그러나 1D 형태인 1D SPIHT은 래스터 주사 순서에 적합함에도 관련 연구가 많이 진행되지 않았다. 본 논문은 1D SPIHT의 가장 큰 문제점인 속도 문제를 해결할 수 있는 하드웨어 구조를 제안한다. 이를 위해 1D SPIHT 알고리즘은 병렬성을 이용할 수 있는 형태로 수정된다. 인코더의 경우 병렬 처리를 방해하는 의존 관계가 해결되고, 파이프라인 스케쥴링이 가능하게 된다. 디코더의 경우 병렬로 동작하는 각 패스가 디코딩할 비트스트림의 길이를 미리 예측할 수 있도록 알고리즘이 수정된다. 고충실도(high-fidelity) RGBW 컬러 이미지 압축을 위한 방식으로는 예측 기반의 압축 방식을 제안하도록 한다. 제안 예측 방식은 두 단계의 차분 과정으로 구성된다. 첫 번째는 공간적 연관성을 이용하는 단계이고, 두 번째는 인터-컬러 연관성을 이용하는 단계이다. 코딩의 경우 압축 효율이 높은 VLC(variable length coding) 방식을 이용하도록 한다. 그러나 기존의 VLC 방식은 목표 압축률을 정확히 맞추는데 어려움이 있었으므로 본 논문에서는 Golomb-Rice 코딩을 기반으로 한 고정 길이 압축 방식을 제안하도록 한다. 제안 인코더는 프리-코더와 포스터-코더로 구성되어 있다. 프리-코더는 특정 상황에 대하여 실제 인코딩을 수행하고, 다른 모든 상황에 대한 예측 인코딩 정보를 계산하여 포스터-코더에 전달한다. 그리고 포스트-코더는 전달받은 정보를 이용하여 실제 비트스트림을 생성한다.제 1 장 서론 1 1.1 연구 배경 1 1.2 연구 내용 4 1.3 논문 구성 8 제 2 장 이전 연구 9 2.1 BTC 9 2.1.1 기본 BTC 알고리즘 9 2.1.2 컬러 이미지 압축을 위한 BTC 알고리즘 10 2.2 SPIHT 13 2.2.1 1D SPIHT 알고리즘 13 2.2.2 SPIHT 하드웨어 17 2.3 예측 기반 코딩 19 2.3.1 예측 방법 19 2.3.2 VLC 20 2.3.3 예측 기반 코딩 하드웨어 22 제 3 장 LCD 오버드라이브를 위한 BTC 24 3.1 제안 알고리즘 24 3.1.1 비트-절약 방법 25 3.1.2 블록 크기 선택 방법 29 3.1.3 알고리즘 요약 31 3.2 하드웨어 구조 33 3.2.1 프레임 메모리 인터페이스 34 3.2.2 인코더와 디코더의 구조 37 3.3 실험 결과 44 3.3.1 알고리즘 성능 44 3.3.2 하드웨어 구현 결과 49 제 4 장 저비용 근접-무손실 프레임 메모리 압축을 위한 고속 1D SPIHT 54 4.1 인코더 하드웨어 구조 54 4.1.1 의존 관계 분석 및 제안하는 파이프라인 스케쥴 54 4.1.2 분류 비트 재배치 57 4.2 디코더 하드웨어 구조 59 4.2.1 비트스트림의 시작 주소 계산 59 4.2.2 절반-패스 처리 방법 63 4.3 하드웨어 구현 65 4.4 실험 결과 73 제 5 장 고충실도 RGBW 컬러 이미지 압축을 위한 고정 압축비 VLC 81 5.1 제안 알고리즘 81 5.1.1 RGBW 인터-컬러 연관성을 이용한 예측 방식 82 5.1.2 고정 압축비를 위한 Golomb-Rice 코딩 85 5.1.3 알고리즘 요약 89 5.2 하드웨어 구조 90 5.2.1 인코더 구조 91 5.2.2 디코더 구조 95 5.3 실험 결과 101 5.3.1 알고리즘 실험 결과 101 5.3.2 하드웨어 구현 결과 107 제 6 장 압축 성능 및 하드웨어 크기 비교 분석 113 6.1 압축 성능 비교 113 6.2 하드웨어 크기 비교 120 제 7 장 결론 125 참고문헌 128 ABSTRACT 135Docto

A High-Performance Data Acquisition System for Smart Cameras in Science

This dissertation proposes a novel smart camera platform serving as a flexible data acquisition system for scientific applications. Current technological progress offers increasing performance in the areas we consider, namely high data-throughput, data processing, and detector performance. Prevalent data acquisition solutions typically focus on one of these aspects. However, driven by science, experiments experience increasing demands in terms of data throughput, speed and flexibility. In this dissertation, we introduce a system which, in addition to being able to provide high-speed data transfer, is also capable of interpreting the incoming information at an early stage. In order to demonstrate the full potential of the smart camera platform, we focus on X-ray imaging with synchrotron light sources. X-ray imaging applications can investigate the traits of technological and biological processes over microseconds for radiography, and milliseconds for tomography applications. These applications may require different sensors, and include complex experiment operations. The new smart camera platform is part of a larger project, UFO, which introduces a new concept for X-ray imaging. On-line data assessment is used to provide a data-driven feedback and active management of both the process and data acquisition procedure. This is accomplished using a GPU platform for fast reconstruction, embedded on-camera data processing, and integrating smart camera in a high-throughput data acquisition system. The final design of the smart camera platform consists of a custom high-performance FPGA board, providing continuous data transfer, embedded image processing, and a flexible input stage. In the IMAGE beamline of ANKA, camera is integrated in the new control system, and used in real-life applications. A maximum data-throughput of up to 8 GB/s is achieved. A custom image-based algorithm is implemented in the FPGA, with stringent real-time requirements, able to increase native sensor speed up to five times while reducing the amount of transfered data. Several image sensors are used, with resolutions of up to 20 megapixels and frame rates of up to 5 kfps. The smart camera platform was also used in non-imaging applications, stemming from the flexible input stage. The proposed camera architecture enables the user to modify the current system for any kind of high data-throughput applications, and to modify and implement custom processing algorithms

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer

Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments

RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer