Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each cell also has an 8-bit configuration register which allows masking, test-enabling and 3-bit individual threshold adjust for each discriminator. The chip can be configured in serial mode and readout either serially or in parallel. Measurements show an electronic noise ~160 e- rms with a gain of ~9 mV/ke-. The threshold spread after equalization of ~120 e- rms brings the full chip minimum detectable charge to ~1100 e-. The analog static power consumption is ~8 µW per pixel with Vdda=2.2 V. The Mpix2MXR20 is an upgraded version of the Medipix2. The main changes in the pixel consist of: an improved tolerance to radiation, improved pixel to pixel threshold uniformity, and a 14-bit counter with overflow control. The chip periphery includes new threshold DACs with smaller step size, improved linearity, and better temperature dependence. Timepix is an evolution of the Mpix2MXR20 which provides independently in each pixel information of arrival time, time-over-threshold or event counting. Timepix uses as a time reference an external clock (Ref_Clk) up to 100 MHz which is distributed all over the pixel matrix during acquisition mode. The preamplifier is improved and there is a single discriminator with 4-bit threshold adjustment in order to reduce the minimum detectable charge limit. Measurements show an electrical noise ~100 e- rms and a gain of ~16.5 mV/ke-. The threshold spread after equalization of ~35 e- rms brings the full chip minimum detectable charge either to ~650 e- with a naked chip (i.e. gas detectors) or ~750 e- when bump-bonded to a detector. The pixel static power consumption is ~13.5 µW per pixel with Vdda=2.2 V and Ref_Clk=80 MHz. This family of chips have been used for a wide variety of applications. During these studies a number of limitations have come to light. Among those are limited energy resolution and surface area. Future developments, such as Medipix3, will aim to address those limitations by carefully exploiting developments in microelectronics

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Ultra high-density hybrid pixel sensors for the detection of charge particles

L'abstract è presente nell'allegato / the abstract is in the attachmen

Optimization Tools for ConvNets on the Edge

L'abstract è presente nell'allegato / the abstract is in the attachmen

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Development and Characterisation of a Radiation Hard Readout Chip for the LHCb-Experiment

Within this doctoral thesis parts of the radiation hard readout chip Beetle have been developed and characterised, before and after irradiation. The design work included the analogue memory with the corresponding readout amplifier as well as components of the digital control circuitry. An interface compatible with the I2C-standard and the control logic for event readout have been implemented. A scheme has been developed which ensures the robustness of the Beetle chip against Single Event Upset (SEU). This includes the consistent use of triple-redundant memory devices together with a self-triggered correction in parts of the circuit. The Beetle ASIC is a 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier and a CR-RC pulse shaper. It features an equivalent noise charge of ENC = 497 e + 48.3 e/pF Cin. The analogue memory is a switched capacitor array, which provides a latency of max. 4 us. The 128 channels are transmitted off chip in 900 ns via a current driver. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. A total ionising dose irradiation of Beetle1.1 up to 45 Mrad showed no functional failure and only slight degradation in the analogue performance. Chip version 1.2 fulfils the requirements of the vertex detector (VELO), the inner tracker (ITR) and the RICH detectors of the LHCb experiment