Self-routing lowest common ancestor networks

Multistage interconnection networks (MIN's) allow communication between terminals on opposing sides of a network. Lowest Common Ancestor Networks (LCAN's) [1] have switches capable of connecting bi-directional links in a permutation pattern that additionally permits communication between terminals on the same side. Self-routing LCAN's have interesting permutation routing capabilities and are highly partionable. This paper characterizes self-routing LCAN's and analyzes their permutation routing capabilities. It is shown that the routing network of the CM-5 is a particular instance of an LCAN

Shortest path routing algorithm for hierarchical interconnection network-on-chip

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=logn4-2 and k>0, in worst case to determine the next node along the shortest path

Adaptive routing algorithm in x-Folded TM topology

In recent days, more complicated interconnection topologies have been replaced with previously simple topologies that also exhibit high performance. x-Folded TM network is a TM network that is folded according to the imaginary x-Axis in interconnection networks. For a x-Folded TM network, there is a reduction in the average distance and diameter which corroborates the efficient performance. Also many routing algorithms can be applied to interconnection network for the efficient use of network resources. This paper presents the effectiveness of the x-Folded TM network with the average latency and network throughput under the adaptive routing algorithm to improve dynamic communication performance. We evaluate the communication performance with simulating the topology under the adaptive routing algorithm. It is found from the result that the performance of a x-Folded TM network has been improved compared with other topologies

A challenge for routing algorithms in optical multistage interconnection networks

Problem statement: A class of dynamic interconnection networks is Multistage Interconnection Networks (MINs) that connects input devices to output devices through a number of switch stages. MINs have assumed importance in recent years; because of their cost-effectiveness. Optical MINs are one type of MINs that have large transmission capacity in the communication networks. There is a major problem in Optical MIN that is crosstalk, which is caused by coupling two signals within a switching element. Approach: To avoid crosstalk in Optical MINs many algorithms have been proposed by many researchers that we review applying five routing algorithms and scheduling them in the Optical MINs. Results: The comparative results of routing algorithms show affective of avoiding crosstalk in number of passes and execution time for different algorithm. Conclusion: The challenge between these routing algorithms is thoroughly investigated, by applying them on Optical MIN and showing which algorithm has better performance to avoid crosstalk

Topology Architecture and Routing Algorithms of Octagon-Connected Torus Interconnection Network

Two important issues in the design of interconnection networks for massively parallel computers are scalability and small diameter. A new interconnection network topology, called octagon-connected torus (OCT), is proposed. The OCT network combines the small diameter of octagon topology and the scalability of torus topology. The OCT network has better properties, such as small diameter, regular, symmetry and the scalability. The nodes of the OCT network adopt the Johnson coding scheme which can make routing algorithms simple and efficient. Both unicasting and broadcasting routing algorithms are designed for the OCT network, and it is based on the Johnson coding scheme. A detailed analysis shows that the OCT network is a better interconnection network in the properties of topology and the performance of communication

On Optimal Placements of Processors in Tori Networks

Two and three dimensional k-tori are among the most used topologies in the design of new parallel computers. Traditionally (with the exception of the Tera parallel computer), these networks have been used as fully-populated networks, in the sense that every routing node in the topology is subjected to message injection. However, fully-populated tori and meshes exhibit a theoretical throughput which degrades as the network size increases. In addition, the performance of those networks is sensitive to link faults. In contrast, multistage networks (that are partially populated) scale well with the network size. We propose to add slackness in fully-populated tori by reducing the number of processors and we study optimal fault-tolerant routing strategies for the resulting interconnections. The key concept that we study is the average link load in an interconnection network with a given placement and a routing algorithm, where a placement is the subset of the nodes in the interconnection network that are attached to processors. Reducing the load on the links by the choice of a placement and a routing algorithm leads to improvements in both the performance and the fault tolerance of the communication system. Our main contribution is the construction of optimal placements for 2 and 3-dimensional k-tori networks and their corresponding routing algorithms. Those placements yield a linear (in the number of processors) link load and are of optimal size

Lowest common ancestor interconnection networks

Lowest Common Ancestor (LCA) networks are built using switches capable of connecting u + d inputs/outputs in a permutation pattern. For n source nodes and I stages of switches, n/d switches are used in stage l - n/d - u/d in stage l - 2, and in general , n-u^l-i-l/d^l-i switches in stage i. The resulting hierarchical structure possesses interesting connectivity and permutational properties. A full characterization of LCA networks is presented together with a permutation routing algorithm for a family of LCA networks. The algorithm uses the network itself to collect and disseminate information about the permutation. A schedule of O(dp log_d/u n) passes is obtained with a switch set-up cost factor of O(log_d/u n) (p is the minimum number of passes that an algorithm with global knowledge schedules)