Building Blocks for Adaptive Modular Sensing Systems

This thesis contributes towards the development of systems and strategies by which sensor and actuator components can be combined to produce flexible and robust sensor systems for a given application. A set of intelligent modular blocks (building blocks) have been created from which composite sensors (made up of multiple sensor and actuator components) can be rapidly reconfigured for the construction of Adaptive Modular Sensing Systems. The composite systems are expected to prove useful in several application domains including industrial control, inspection systems, mobile robotics, monitoring and data acquisition. The intelligent building blocks, referred to as transducer interface modules, contain embedded knowledge about their capabilities and how they can interact with other modules. These modules encapsulate a general purpose modular hardware architecture that provides an interface between the sensors, the actuators, and the communication medium. The geometry of each transducer interface module is a cube. A connector mechanism implemented on each face of the module enables physical connection of the modules. Each module provides a core functionality and can be connected to other modules to form more capable composite sensors. Once the modules are combined, the capabilities (e.g., range, resolution, sample rate, etc.) and functionality (e.g., temperature measurement) of the composite sensor is determined and communicated to other sensors in the enviornment. For maximum flexibility, a distributed software architecture is executed on the blocks to enable automatic acquisition of configuration-specific algorithms. This logical algorithm imparts a collective identity to the composite group, and processes data based on the capabilities and functionalities of the transducers present in the system. A knowledge representation scheme allows each module in the composite group to store and communicate its functionality and capabilities to other connected modules in the system

Center for Aeronautics and Space Information Sciences

This report summarizes the research done during 1991/92 under the Center for Aeronautics and Space Information Science (CASIS) program. The topics covered are computer architecture, networking, and neural nets

Doctor of Philosophy

dissertationThe embedded system space is characterized by a rapid evolution in the complexity and functionality of applications. In addition, the short time-to-market nature of the business motivates the use of programmable devices capable of meeting the conflicting constraints of low-energy, high-performance, and short design times. The keys to achieving these conflicting constraints are specialization and maximally extracting available application parallelism. General purpose processors are flexible but are either too power hungry or lack the necessary performance. Application-specific integrated circuits (ASICS) efficiently meet the performance and power needs but are inflexible. Programmable domain-specific architectures (DSAs) are an attractive middle ground, but their design requires significant time, resources, and expertise in a variety of specialties, which range from application algorithms to architecture and ultimately, circuit design. This dissertation presents CoGenE, a design framework that automates the design of energy-performance-optimal DSAs for embedded systems. For a given application domain and a user-chosen initial architectural specification, CoGenE consists of a a Compiler to generate execution binary, a simulator Generator to collect performance/energy statistics, and an Explorer that modifies the current architecture to improve energy-performance-area characteristics. The above process repeats automatically until the user-specified constraints are achieved. This removes or alleviates the time needed to understand the application, manually design the DSA, and generate object code for the DSA. Thus, CoGenE is a new design methodology that represents a significant improvement in performance, energy dissipation, design time, and resources. This dissertation employs the face recognition domain to showcase a flexible architectural design methodology that creates "ASIC-like" DSAs. The DSAs are instruction set architecture (ISA)-independent and achieve good energy-performance characteristics by coscheduling the often conflicting constraints of data access, data movement, and computation through a flexible interconnect. This represents a significant increase in programming complexity and code generation time. To address this problem, the CoGenE compiler employs integer linear programming (ILP)-based 'interconnect-aware' scheduling techniques for automatic code generation. The CoGenE explorer employs an iterative technique to search the complete design space and select a set of energy-performance-optimal candidates. When compared to manual designs, results demonstrate that CoGenE produces superior designs for three application domains: face recognition, speech recognition and wireless telephony. While CoGenE is well suited to applications that exhibit a streaming behavior, multithreaded applications like ray tracing present a different but important challenge. To demonstrate its generality, CoGenE is evaluated in designing a novel multicore N-wide SIMD architecture, known as StreamRay, for the ray tracing domain. CoGenE is used to synthesize the SIMD execution cores, the compiler that generates the application binary, and the interconnection subsystem. Further, separating address and data computations in space reduces data movement and contention for resources, thereby significantly improving performance compared to existing ray tracing approaches

Performance Comparison of PSO and Its New Variants in the Context of VLSI Global Routing

Substantial reduction of gate delay occurred in recent times owing to radical decrement of transistor size. The interconnect length and delay are accordingly increased owing to the exponential escalation of packaging density with additional transistors being fabricated on the same chip area. The function of VLSI routing that seems to be more defying to the scholars, is categorized in global routing and detailed routing phase. In global routing phase, the prevalent method to lessen the wire length for reducing interconnect delay is to adjust the cost of the Steiner tree, devised by the terminal nodes to be interconnected. Nevertheless, Steiner tree problem is a NP-complete problem in classical graph theory where meta-heuristics might impart beneficial elucidations. Particle swarm optimization (PSO) is a robust algorithm concerning VLSI routing field. This chapter is regarding the proposal of a self-adaptive mechanism for monitoring acceleration coefficient of PSO and evaluating its functionalities with the existing acceleration coefficient controlled PSO in numerous allocation topologies of terminal nodes within definite VLSI layout. The outcomes of PSO variant with constriction factor in context to VLSI route reduction ability and robustness are also inspected. Additionally, a new effort in adapting the PSO with embracement of genetic algorithm is established

Amorphous Medium Language

Programming reliable behavior on a large mesh network composed of unreliable parts is difficult. Amorphous Medium Language addresses this problem by abstracting robustness and networking issues away from the programmer via language of geometric primitives and homeostasis maintenance.AML is designed to operate on a high diameter network composed of thousands to billions of nodes, and does not assume coordinate, naming, or routing services. Computational processes are distributed through geometric regions of the space approximated by the network and specify behavior in terms of homeostasis conditions and actions to betaken when homeostasis is violated.AML programs are compiled for local execution using previously developed amorphous computing primitives which provide robustness against ongoing failures and joins and localize the impact of changes in topology. I show some examples of how AML allows complex robust behavior to be expressed in simple programs and some preliminary results from simulation