93 research outputs found
Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference
A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative âiterativeâ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply
Low-voltage tunable pseudo-differential transconductor with high linearity
A novel tunable transconductor is presented. Input
transistors operate in the triode region to achieve
programmable voltage-to-current conversion. These
transistors are kept in the triode region by a novel
negative feedback loop which features simplicity, low
voltage requirements, and high output resistance. A
linearity analysis is carried out which demonstrates how
the proposed transconductance tuning scheme leads to
high linearity in a wide transconductance range.
Measurement results for a 0.5 ÎŒm CMOS implementation
of the transconductor show a transconductance tuning
range of more than a decade (15 ÎŒA/V to 165 ÎŒA/V) and a
total harmonic distortion of â67 dB at 1 MHz for an input
of 1 Vpp and a supply voltage of 1.8 V
High Performance Integrated Circuit Blocks for High-IF Wideband Receivers
Due to the demand for highâperformance radio frequency (RF) integrated circuit
design in the past years, a systemâonâchip (SoC) that enables integration of analog and
digital parts on the same die has become the trend of the microelectronics industry. As
a result, a major requirement of the next generation of wireless devices is to support
multiple standards in the same chipâset. This would enable a single device to support
multiple peripheral applications and services.
Based on the aforementioned, the traditional superheterodyne frontâend
architecture is not suitable for such applications as it would require a complete receiver
for each standard to be supported. A more attractive alternative is the highintermediate
frequency (IF) radio architecture. In this case the signal is digitalized at an
intermediate frequency such as 200MHz. As a consequence, the baseband operations,
such as downâconversion and channel filtering, become more power and area efficient
in the digital domain. Such architecture releases the specifications for most of the frontâend building blocks, but the linearity and dynamic range of the ADC become the
bottlenecks in this system. The requirements of large bandwidth, high frequency and
enough resolution make such ADC very difficult to realize. Many ADC architectures
were analyzed and ContinuousâTime Bandpass SigmaâDelta (CTâBPâÎŁÎ) architecture was
found to be the most suitable solution in the highâIF receiver architecture since they
combine oversampling and noise shaping to get fairly high resolution in a limited
bandwidth.
A major issue in continuousâtime networks is the lack of accuracy due to powervoltageâ
temperature (PVT) tolerances that lead to over 20% pole variations compared
to their discreteâtime counterparts. An optimally tuned BP ÎŁÎ ADC requires correcting
for center frequency deviations, excess loop delay, and DAC coefficients. Due to these
undesirable effects, a calibration algorithm is necessary to compensate for these
variations in order to achieve high SNR requirements as technology shrinks.
In this work, a novel linearization technique for a Wideband LowâNoise
Amplifier (LNA) targeted for a frequency range of 3â7GHz is presented. Postâlayout
simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm,
respectively. The power consumption of the LNA is 5.8mA from 2V.
Secondly, the design of a CMOS 6th order CT BPâÎŁÎ modulator running at 800
MHz for HighâIF conversion of 10MHz bandwidth signals at 200 MHz is presented. A
novel transconductance amplifier has been developed to achieve high linearity and high
dynamic range at high frequencies. A 2âbit quantizer with offset cancellation is alsopresented. The sixthâorder modulator is implemented using 0.18 um TSMC standard
analog CMOS technology. Postâlayout simulations in cadence demonstrate that the
modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth.
The modulatorâs static power consumption is 107mW from a supply power of ± 0.9V.
Finally, a calibration technique for the optimization of the Noise Transfer
Function CT BP ÎŁÎ modulators is presented. The proposed technique employs two test
tones applied at the input of the quantizer to evaluate the noise transfer function of
the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually
available in mixedâmode systems. Once the ADC output bit stream is captured,
necessary information to generate the control signals to tune the ADC parameters for
best SignalâtoâQuantization Noise Ratio (SQNR) performance is extracted via Leastâ
Mean Squared (LMS) softwareâbased algorithm. Since the two tones are located
outside the band of interest, the proposed global calibration approach can be used
online with no significant effect on the inâband content
Systematic Comparison of HF CMOS Transconductors
Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments
A low-pass filter with automatic frequency tuning for a bluetooth receiver
A third-order Gm-C Chebyshev low-pass filter with high
linearity and automatic frequency programmability has been
designed. The filter is intended to be used as a channel-select
filter for a zero-IF Bluetooth receiver. The frequency tuning
scheme is simpler and has more relaxed specifications than
conventional ones. The filter bandwidth is 0.5 MHz and the
overall scheme dissipates 1.1 mA from a 1.8-V supply. The
third-order intermodulation (IM3) distortion of the filter for a
1Vpp two-tone signal centered at 350 kHz is â67dB
A low-pass filter with automatic frequency tuning for a bluetooth receiver
A third-order Gm-C Chebyshev low-pass filter with high linearity and automatic frequency programmability has been designed. The filter is intended to be used as a channel-select filter for a zero-IF Bluetooth receiver. The frequency tuning scheme is simpler and has more relaxed specifications than conventional ones. The filter bandwidth is 0.5 MHz and the overall scheme dissipates 1.1 mA from a 1.8-V supply. The third-order intermodulation (IM3) distortion of the filter for a 1Vpp two-tone signal centered at 350 kHz is -67dB.Ministerio de Ciencia y TecnologĂa TEC2007-67460-C03-02
High frequency and high dynamic range continuous time filters
Many modern communication systems use orthogonal frequency division
multiplexing (OFDM) and discrete multi-tone (DMT) as modulation schemes where
high data rates are transmitted over a wide frequency band in multiple orthogonal subcarriers.
Due to the many advantages, such as flexibility, good noise immunity and the
ability to be optimized for medium conditions, the use of DMT and OFDM can be found
in digital video broadcasting, local area wireless network (IEEE 802.11a), asymmetric
digital subscriber line (ADSL), very high bit rate DSL (VDSL) and power line
communications (PLC). However, a major challenge is the design of the analog frontend;
for these systems a large dynamic range is required due to the significant peak to
average ratio of the resulting signals. In receivers, very demanding high-performance
analog filters are typically used to block interferers and provide anti-aliasing before the
subsequent analog to digital conversion stage. For frequencies higher than 10MHz, Gm-C filter implementations are generally
preferred due to the more efficient operation of wide-band operational transconductance
amplifiers (OTA). Nevertheless, the inherent low-linearity of open-loop operated OTA
limits the dynamic range. In this dissertation, three different proposed OTA linearity
enhancement techniques for the design of high frequency and high dynamic range are
presented. The techniques are applied to two filter implementations: a 20MHz second
order tunable filter and a 30MHz fifth order elliptical low-pass filter. Simulation and
experimental results show a spurious free dynamic range (SFDR) of 65dB with a power
consumption of 85mW. In a figure of merit where SFDR is normalized to the power
consumption, this filter is 6dB above the trend-line of recently reported continuous time
filters
Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits
High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption.
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth.
Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power.
High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels
Digitally Assisted Adaptive Non-Linearity Suppression Scheme for RF front ends
This paper presents a robust and low-complexity non-linearity suppression scheme for radio frequency (RF) transceiver building blocks to efficiently mitigate intermodulation distortion. The scheme consists of tunable RF components assisted by an auxiliary path equipped with an adaptive digital signal processing algorithm to provide the tuning control. This proposed concept of digitally-assisted tuning is capable of handling a large range of non-linear behaviours without any complexity increase in the expensive RF circuitry and is robust to process, voltage and temperature variations. A case study on the third order intermodulation of the channel select filter for a full 10 MHz Long Term Evolution (LTE) reception bandwidth is used to demonstrate the feasibility and effectiveness of the technique
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