1-Bit Massive MIMO Downlink Based on Constructive Interference

In this paper, we focus on the multiuser massive multiple-input single-output (MISO) downlink with low-cost 1-bit digital-to-analog converters (DACs) for PSK modulation, and propose a low-complexity refinement process that is applicable to any existing 1-bit precoding approaches based on the constructive interference (CI) formulation. With the decomposition of the signals along the detection thresholds, we first formulate a simple symbol-scaling method as the performance metric. The low-complexity refinement approach is subsequently introduced, where we aim to improve the introduced symbol-scaling performance metric by modifying the transmit signal on one antenna at a time. Numerical results validate the effectiveness of the proposed refinement method on existing approaches for massive MIMO with 1-bit DACs, and the performance improvements are most significant for the low-complexity quantized zero-forcing (ZF) method.Comment: 5 pages, EUSIPCO 201

Comparative Analysis among DSP and FPGA-based Control Capabilities in PWM Power Converters

PWM power converters are close to be mature for standard diffusion. New FPGA technologies could now realise at best the digital control key-points: flexible performance and time to market. The paper deals with the new digital control properties of FPGA-based techniques. On the basis of reference structures, a comparative analysis is carried-out trading-off dynamic performances and immunity to PWM environment. All possible sampled control or DSP techniques are firstly analysed and compared to each other. A breakthrough concept for FPGAs is defined, definitely solving for PWM feedback immunity by practical over-sampling and parallel processing while improving dynamic performances. Simulation tests and the application of dead-beat control clearly point-out the respective dynamic properties

MMSE precoder for massive MIMO using 1-bit quantization

We propose a novel linear minimum-mean-squared-error (MMSE) precoder design for a downlink (DL) massive multiple-input-multiple-output (MIMO) scenario. For economical and computational efficiency reasons low resolution 1-bit digital-to-analog (DAC) and analog-to-digital (ADC) converters are used. This comes at the cost of performance gain that can be recovered by the large number of antennas deployed at the base station (BS) and an appropiate precoder design to mitigate the distortions due to the coarse quantization. The proposed precoder takes the quantization non-linearities into account and is split into a digital precoder and an analog precoder. We formulate the two-stage precoding problem such that the MSE of the users is minimized under the 1-bit constraint. In the simulations, we compare the new optimized precoding scheme with previously proposed linear precoders in terms of uncoded bit error ratio (BER).Comment: Presented in ICASSP 2016, 20-25 March 2016, Shanghai, Chin

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin

MMSE precoder for massive MIMO using 1-bit quantization

We propose a novel linear minimum-mean-squared-error (MMSE) precoder design for a downlink (DL) massive multiple-input-multiple-output (MIMO) scenario. For economical and computational efficiency reasons low resolution 1-bit digital-to-analog (DAC) and analog-to-digital (ADC) converters are used. This comes at the cost of performance gain that can be recovered by the large number of antennas deployed at the base station (BS) and an appropiate precoder design to mitigate the distortions due to the coarse quantization. The proposed precoder takes the quantization non-linearities into account and is split into a digital precoder and an analog precoder. We formulate the two-stage precoding problem such that the MSE of the users is minimized under the 1-bit constraint. In the simulations, we compare the new optimized precoding scheme with previously proposed linear precoders in terms of uncoded bit error ratio (BER).Comment: Presented in ICASSP 2016, 20-25 March 2016, Shanghai, Chin

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.Comment: 15 pages, contribution to the 2014 CAS - CERN Accelerator School: Power Converters, Baden, Switzerland, 7-14 May 201

Phased Array Systems in Silicon

Phased array systems, a special case of MIMO systems, take advantage of spatial directivity and array gain to increase spectral efficiency. Implementing a phased array system at high frequency in a commercial silicon process technology presents several challenges. This article focuses on the architectural and circuit-level trade-offs involved in the design of the first silicon-based fully integrated phased array system operating at 24 GHz. The details of some of the important circuit building blocks are also discussed. The measured results demonstrate the feasibility of using integrated phased arrays for wireless communication and vehicular radar applications at 24 GHz

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879