Automated Quantum Oracle Synthesis with a Minimal Number of Qubits

Several prominent quantum computing algorithms--including Grover's search algorithm and Shor's algorithm for finding the prime factorization of an integer--employ subcircuits termed 'oracles' that embed a specific instance of a mathematical function into a corresponding bijective function that is then realized as a quantum circuit representation. Designing oracles, and particularly, designing them to be optimized for a particular use case, can be a non-trivial task. For example, the challenge of implementing quantum circuits in the current era of NISQ-based quantum computers generally dictates that they should be designed with a minimal number of qubits, as larger qubit counts increase the likelihood that computations will fail due to one or more of the qubits decohering. However, some quantum circuits require that function domain values be preserved, which can preclude using the minimal number of qubits in the oracle circuit. Thus, quantum oracles must be designed with a particular application in mind. In this work, we present two methods for automatic quantum oracle synthesis. One of these methods uses a minimal number of qubits, while the other preserves the function domain values while also minimizing the overall required number of qubits. For each method, we describe known quantum circuit use cases, and illustrate implementation using an automated quantum compilation and optimization tool to synthesize oracles for a set of benchmark functions; we can then compare the methods with metrics including required qubit count and quantum circuit complexity.Comment: 18 pages, 10 figures, SPIE Defense + Commercial Sensing: Quantum Information Science, Sensing, and Computation X

Decomposition tool targeting FPGA architectures

The growing interest in the field of logic synthesis targeting Field Programmable Gate Arrays (FPGA) and the active research carried out by a number of research groups in the area of functional decomposition is the prime motivation for this thesis. Logic synthesis has been an area of interest in many universities all over the world. The work involves the study and implementation of techniques and methods in logic synthesis. In this work, a logic synthesis tool has been developed implementing the aspects of general and complete Decomposition method based on functional decomposition techniques [4]. The tool is aimed at producing outputs faster and more efficient than the available software. C++ Standard template library is used to develop this tool. The output of this tool is designed to be compatible with the available vendor software. The tool has been tested on MCNC benchmarks and those created keeping in mind the industry requirements

Division-based versus general decomposition-based multiple-level logic synthesis

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem with different minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-based approach. However, modem microelectronic technology provides a large variety of building blocks which considerably differ from those typically considered. The traditional methods are therefore not suitable for synthesis with many modem building blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered some important design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, other ones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by the microelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare the general decomposition approach and the division-based approach. The most important advantages of the general decomposition approach are its generality (any network of any building blocks can be considered) and totality (all important design aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases, the general decomposition approach gives much better results than the traditional approaches

Logic synthesis and optimisation using Reed-Muller expansions

This thesis presents techniques and algorithms which may be employed to represent, generate and optimise particular categories of Exclusive-OR SumOf-Products (ESOP) forms. The work documented herein concentrates on two types of Reed-Muller (RM) expressions, namely, Fixed Polarity Reed-Muller (FPRM) expansions and KROnecker (KRO) expansions (a category of mixed polarity RM expansions). Initially, the theory of switching functions is comprehensively reviewed. This includes descriptions of various types of RM expansion and ESOP forms. The structure of Binary Decision Diagrams (BDDs) and Reed-Muller Universal Logic Module (RM-ULM) networks are also examined. Heuristic algorithms for deriving optimal (sub-optimal) FPRM expansions of Boolean functions are described. These algorithms are improved forms of an existing tabular technique [1]. Results are presented which illustrate the performance of these new minimisation methods when evaluated against selected existing techniques. An algorithm which may be employed to generate FPRM expansions from incompletely specified Boolean functions is also described. This technique introduces a means of determining the optimum allocation of the Boolean 'don't care' terms so as to derive equivalent minimal FPRM expansions. The tabular technique [1] is extended to allow the representation of KRO expansions. This new method may be employed to generate KRO expansions from either an initial incompletely specified Boolean function or a KRO expansion of different polarity. Additionally, it may be necessary to derive KRO expressions from Boolean Sum-Of-Products (SOP) forms where the product terms are not minterms. A technique is described which forms KRO expansions from disjoint SOP forms without first expanding the SOP expressions to minterm forms. Reed-Muller Binary Decision Diagrams (RMBDDs) are introduced as a graphical means of representing FPRM expansions. RMBDDs are analogous to the BDDs used to represent Boolean functions. Rules are detailed which allow the efficient representation of the initial FPRM expansions and an algorithm is presented which may be employed to determine an optimum (sub-optimum) variable ordering for the RMBDDs. The implementation of RMBDDs as RM-ULM networks is also examined. This thesis is concluded with a review of the algorithms and techniques developed during this research project. The value of these methods are discussed and suggestions are made as to how improved results could have been obtained. Additionally, areas for future work are proposed

Синтез k-значных цифровых IP-модулей для роботов и датчиковых систем на основе линейных преобразований токовых логических сигналов

The paper presents the results of studies of a double-valued and a multi-valued elements stock (ES) for digital structures, including robots and flying vehicles, that operates by using linear transformations of current logic signals. A goal of the studies is to develop methods of synthesis and analog circuits engineering solutions of the alternative digital ES with the improved (as compared to the traditional elements stock) technical, technological and operational characteristics.Приведены результаты исследования двузначной и многозначной элементной базы (ЭБ) для цифровых структур, в т.ч. роботов и летательных аппаратов, функционирующей на основе линейных преобразований токовых логических сигналов. Цель исследований — разработка методов синтеза и аналоговых схемотехнических решений альтернативной цифровой ЭБ с улучшенными (в сравнении с традиционной элементной базой) техническими, технологическими и эксплуатационными характеристиками

Compact DSOP and partial DSOP Forms

Given a Boolean function f on n variables, a Disjoint Sum-of-Products (DSOP) of f is a set of products (ANDs) of subsets of literals whose sum (OR) equals f, such that no two products cover the same minterm of f. DSOP forms are a special instance of partial DSOPs, i.e. the general case where a subset of minterms must be covered exactly once and the other minterms (typically corresponding to don't care conditions of $f$) can be covered any number of times. We discuss finding DSOPs and partial DSOP with a minimal number of products, a problem theoretically connected with various properties of Boolean functions and practically relevant in the synthesis of digital circuits. Finding an absolute minimum is hard, in fact we prove that the problem of absolute minimization of partial DSOPs is NP-hard. Therefore it is crucial to devise a polynomial time heuristic that compares favorably with the known minimization tools. To this end we develop a further piece of theory starting from the definition of the weight of a product p as a functions of the number of fragments induced on other cubes by the selection of p, and show how product weights can be exploited for building a class of minimization heuristics for DSOP and partial DSOP synthesis. A set of experiments conducted on major benchmark functions show that our method, with a family of variants, always generates better results than the ones of previous heuristics, including the method based on a BDD representation of f

Automated synthesis and optimization of multilevel logic circuits.

With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synthesis plays an even more important role due to its flexibility and compactness.The history of symbolic logic and some typical techniques for multilevel logic synthesisare reviewed. These methods include algorithmic approach; Rule-Based approach; BinaryDecision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approachand several perturbation applications.One new kind of don't cares (DCs), called functional DCs has been proposed for multilevellogic synthesis. The conventional two-level cubes are generalized to multilevel cubes.Then functional DCs are generated based on the properties of containment. The conceptof containment is more general than unateness which leads to the generation of newDCs. A separate C program has been developed to utilize the functional DCs generatedas a Boolean function is decomposed for both single output and multiple output functions.The program can produce better results than script.rugged of SIS, developed by UC Berkeley,both in area and speed in less CPU time for a number of testcases from MCNC andIWLS'93 benchmarks.In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantagesover the standard Boolean logic based on AND JOR operations. A bidirectionalconversion algorithm between these two paradigms is presented based on the concept of polarityfor sum-of-products (SOP) Boolean functions, multiple segment and multiple pointerfacilities. Experimental results show that the algorithm is much faster than the previouslypublished programs for any fixed polarity. Based on this algorithm, a new technique calledredundancy-removal is applied to generalize the idea to very large multiple output Booleanfunctions. Results for benchmarks with up to 199 inputs and 99 outputs are presented.Applying the preceding conversion program, any Boolean functions can be expressedby fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function andthe number of product terms depends on these polarities. The problem of exact polarityminimization is computationally extensive and current programs are only suitable whenn :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logicand Reed-Muller logic, a fast algorithm is developed and implemented in C language whichcan find the best polarity for multiple output functions. Benchmark examples of up to 25inputs and 29 outputs run on a personal computer are given.After the best polarity for a Boolean function is calculated, this function can be furthersimplified using mixed polarity methods by combining the adjacent product terms. Hence,an efficient program is developed based on decomposition strategy to implement mixedpolarity minimization for both single output and very large multiple output Boolean functions.Experimental results show that the numbers of product terms are much less thanthe results produced by ESPRESSO for some categories of functions