LOW POWER MULTIPLIER USING ALGORITHMIC NOISE TOLERANT ARCHITECTURE

: A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis (Ayman.A et al (2001)). Many current DSP applications are targeted at portable, battery-operated systems, so that power dissipation becomes one of the primary design constraints. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. In this project a multiplier block has been designed through the algorithmic noise tolerance architectures (ANT) by using Wallace multiplier. A reliable low power multiplier design with the fixed width multiplier block through the reduced precision replica redundancy (RPR) and main block design with Wallace multiplier . The new architecture can meet the high accuracy, low power consumption and area efficiency when compared with previous multiplier circuit

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit

Design Techniques for Energy-Quality Scalable Digital Systems

Energy efficiency is one of the key design goals in modern computing. Increasingly complex tasks are being executed in mobile devices and Internet of Things end-nodes, which are expected to operate for long time intervals, in the orders of months or years, with the limited energy budgets provided by small form-factor batteries. Fortunately, many of such tasks are error resilient, meaning that they can toler- ate some relaxation in the accuracy, precision or reliability of internal operations, without a significant impact on the overall output quality. The error resilience of an application may derive from a number of factors. The processing of analog sensor inputs measuring quantities from the physical world may not always require maximum precision, as the amount of information that can be extracted is limited by the presence of external noise. Outputs destined for human consumption may also contain small or occasional errors, thanks to the limited capabilities of our vision and hearing systems. Finally, some computational patterns commonly found in domains such as statistics, machine learning and operational research, naturally tend to reduce or eliminate errors. Energy-Quality (EQ) scalable digital systems systematically trade off the quality of computations with energy efficiency, by relaxing the precision, the accuracy, or the reliability of internal software and hardware components in exchange for energy reductions. This design paradigm is believed to offer one of the most promising solutions to the impelling need for low-energy computing. Despite these high expectations, the current state-of-the-art in EQ scalable design suffers from important shortcomings. First, the great majority of techniques proposed in literature focus only on processing hardware and software components. Nonetheless, for many real devices, processing contributes only to a small portion of the total energy consumption, which is dominated by other components (e.g. I/O, memory or data transfers). Second, in order to fulfill its promises and become diffused in commercial devices, EQ scalable design needs to achieve industrial level maturity. This involves moving from purely academic research based on high-level models and theoretical assumptions to engineered flows compatible with existing industry standards. Third, the time-varying nature of error tolerance, both among different applications and within a single task, should become more central in the proposed design methods. This involves designing “dynamic” systems in which the precision or reliability of operations (and consequently their energy consumption) can be dynamically tuned at runtime, rather than “static” solutions, in which the output quality is fixed at design-time. This thesis introduces several new EQ scalable design techniques for digital systems that take the previous observations into account. Besides processing, the proposed methods apply the principles of EQ scalable design also to interconnects and peripherals, which are often relevant contributors to the total energy in sensor nodes and mobile systems respectively. Regardless of the target component, the presented techniques pay special attention to the accurate evaluation of benefits and overheads deriving from EQ scalability, using industrial-level models, and on the integration with existing standard tools and protocols. Moreover, all the works presented in this thesis allow the dynamic reconfiguration of output quality and energy consumption. More specifically, the contribution of this thesis is divided in three parts. In a first body of work, the design of EQ scalable modules for processing hardware data paths is considered. Three design flows are presented, targeting different technologies and exploiting different ways to achieve EQ scalability, i.e. timing-induced errors and precision reduction. These works are inspired by previous approaches from the literature, namely Reduced-Precision Redundancy and Dynamic Accuracy Scaling, which are re-thought to make them compatible with standard Electronic Design Automation (EDA) tools and flows, providing solutions to overcome their main limitations. The second part of the thesis investigates the application of EQ scalable design to serial interconnects, which are the de facto standard for data exchanges between processing hardware and sensors. In this context, two novel bus encodings are proposed, called Approximate Differential Encoding and Serial-T0, that exploit the statistical characteristics of data produced by sensors to reduce the energy consumption on the bus at the cost of controlled data approximations. The two techniques achieve different results for data of different origins, but share the common features of allowing runtime reconfiguration of the allowed error and being compatible with standard serial bus protocols. Finally, the last part of the manuscript is devoted to the application of EQ scalable design principles to displays, which are often among the most energy- hungry components in mobile systems. The two proposals in this context leverage the emissive nature of Organic Light-Emitting Diode (OLED) displays to save energy by altering the displayed image, thus inducing an output quality reduction that depends on the amount of such alteration. The first technique implements an image-adaptive form of brightness scaling, whose outputs are optimized in terms of balance between power consumption and similarity with the input. The second approach achieves concurrent power reduction and image enhancement, by means of an adaptive polynomial transformation. Both solutions focus on minimizing the overheads associated with a real-time implementation of the transformations in software or hardware, so that these do not offset the savings in the display. For each of these three topics, results show that the aforementioned goal of building EQ scalable systems compatible with existing best practices and mature for being integrated in commercial devices can be effectively achieved. Moreover, they also show that very simple and similar principles can be applied to design EQ scalable versions of different system components (processing, peripherals and I/O), and to equip these components with knobs for the runtime reconfiguration of the energy versus quality tradeoff

An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy

Reduced Precision Redundancy (RPR) is a popular Approximate Computing technique, in which a circuit operated in Voltage Over-Scaling (VOS) is paired to a reduced-bitwidth and faster replica so that VOS-induced timing errors are partially recovered by the replica, and their impact is mitigated. Previous works have provided various examples of effective implementations of RPR, which however suffer from three limitations: first, these circuits are designed using ad-hoc procedures, and no generalization is provided; second, error impact analysis is carried out statistically, thus neglecting issues like non-elementary data distribution and temporal correlation. Last, only dynamic power was considered in the optimization. In this work we propose a new generalized approach to RPR that allows to overcome all these limitations, leveraging the capabilities of state-of-the-art synthesis and simulation tools. By sacrificing theoretical provability in favor of an empirical input-based analysis, we build a design tool able to automatically add RPR to a preexisting gate-level netlist. Thanks to this method, we are able to confute some of the conclusions drawn in previous works, in particular those related to statistical assumptions on inputs; we show that a given inputs distribution may yield extremely different results depending on their temporal behavior

DESIGN AND IMPLEMENTATION OF LOW POWER TRUNCATED MULTIPLIER BY ADOPTING ANT ARCHITECTURE USING FIXED-WIDTH RPR BLOCK

The suggested ANT architecture can satisfy the need for high precision, low power consumption, and area efficiency. To reduce the ability dissipation, supply current scaling is broadly used as a good low-power technique because the power consumption in CMOS circuits is proportional towards the square of supply current. While using partial product relation to input correction vector and minor input correction vector to reduce the truncation errors, the hardware complexity of error compensation circuit could be simplified. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Within this paper, we advise a dependable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture using the fixed-width multiplier to construct the lower precision replica redundancy block (RPR). Inside a 12 × 12 bit ANT multiplier, circuit area within our fixed-width RPR could be decreased and power consumption within our ANT design could be saved, in contrast to the condition-of-art ANT design

A CLATTER LIBERAL FRAMEWORK TO CONSTRUCT REPLICA BLOCK

We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. While using partial product relation to input correction vector and minor input correction vector to reduce the truncation errors, the hardware complexity of error compensation circuit could be simplified. Within this paper, we advise a dependable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture using the fixed-width multiplier to construct the lower precision replica redundancy block (RPR). The reduced-current low-power merit within the presented ANT design can nonetheless be preserved under process deviation and-temperature environments. Under lower Kvos, the ability consumption could be decreased. The suggested ANT architecture can satisfy the need for high precision, low power consumption, and area efficiency. Within an ANT multiplier, circuit area within our fixed-width RPR could be decreased and power consumption within our ANT design could be saved compared to the condition-of-art ANT design. The RPR area is yet another main factor which will modify the power saving. The truncated RPRs are examined from word period of 5 to 10 bits using Synopsys design complier CAD tool. Hence, we compare the circuitry area occupied through the fixed-width RPR multiplier and also the full-width RPR multiplier

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

LOW POWER CONSUMED MULTIPLIER DESIGN BY ANT ARCHITECTURE WITH FIXED WIDTH REPLICA REDUNDANCY BLOCK

In this paper, we propose a dependable low-control multiplier configuration by receiving algorithmic commotion tolerant (ANT) engineering with the settled width multiplier to assemble the lessened accuracy copy excess square (RPR). The proposed ANT engineering can take care of the demand of high accuracy, low power utilization, and zone proficiency. We plan the settled width RPR with mistake remuneration circuit by means of examining of likelihood and insights. Utilizing the halfway item terms of information remedy vector and minor info redress vector to bring down the truncation blunders, the equipment unpredictability of mistake pay circuit can be improved. In a 12 × 12 bit ANT multiplier, circuit zone in our settled width RPR can be brought down by 44.55% and control utilization in our ANT configuration can be spared by 23% as contrasted and the condition of-workmanship ANT outline

LOW POWER CONSUMED MULTIPLIER DESIGN BY ANT ARCHITECTURE WITH FIXED WIDTH REPLICA REDUNDANCY BLOCK

In this paper, we propose a dependable low-control multiplier configuration by receiving algorithmic commotion tolerant (ANT) engineering with the settled width multiplier to assemble the lessened accuracy copy excess square (RPR). The proposed ANT engineering can take care of the demand of high accuracy, low power utilization, and zone proficiency. We plan the settled width RPR with mistake remuneration circuit by means of examining of likelihood and insights. Utilizing the halfway item terms of information remedy vector and minor info redress vector to bring down the truncation blunders, the equipment unpredictability of mistake pay circuit can be improved. In a 12 × 12 bit ANT multiplier, circuit zone in our settled width RPR can be brought down by 44.55% and control utilization in our ANT configuration can be spared by 23% as contrasted and the condition of-workmanship ANT outline

Subsurface sounders

Airborne or spaceborne electromagnetic systems used to detect subsurface features are discussed. Data are given as a function of resistivity of ground material, magnetic permeability of free space, and angular frequency. It was noted that resistivities vary with the water content and temperature