Kinetic parameter estimation from TGA: Optimal design of TGA experiments

This work presents a general methodology to determine kinetic models of solid thermal decomposition with thermogravimetric analysis (TGA) instruments. The goal is to determine a simple and robust kinetic model for a given solid with the minimum of TGA experiments. From this last point of view, this work can be seen as an attempt to find the optimal design of TGA experiments for kinetic modelling. Two computation tools were developed. The first is a nonlinear parameter estimation procedure for identifying parameters in nonlinear dynamical models. The second tool computes the thermogravimetric experiment (here, the programmed temperature profile applied to the thermobalance) required in order to identify the best kinetic parameters, i.e. parameters with a higher statistical reliability. The combination of the two tools can be integrated in an iterative approach generally called sequential strategy. The application concerns the thermal degradation of cardboard in a Setaram TGA instrument and the results that are presented demonstrate the improvements in the kinetic parameter estimation process

Gate Oxide Reliability and Deuterated CMOS Processing

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories

The impact of repetitive unclamped inductive switching on the electrical parameters of low-voltage trench power nMOSFETs

The impact of hot-carrier injection (HCI) due to repetitive unclamped inductive switching (UIS) on the electrical performance of low-voltage trench power n-type MOSFETs (nMOSFETs) is assessed. Trench power nMOSFETs with 20- and 30-V breakdown voltage ratings in TO-220 packages have been fabricated and subjected to over 100 million cycles of repetitive UIS with different avalanche currents IAV at a mounting base temperature TMB of 150°C. Impact ionization during avalanche conduction in the channel causes hot-hole injection into the gate dielectric, which results in a reduction of the threshold voltage VGSTX, as the number of avalanche cycles N increases. The experimental data reveal a power-law relationship between the change in the threshold voltage ΔVGSTX and N. The results show that the power-law prefactor is directly proportional to the avalanche current. After 100 million cycles, it was observed in the 20-V rated MOSFETs that the power-law prefactor increased by 30% when IAV was increased from 160 to 225 A, thereby approximating a linear relationship. A stable subthreshold slope with avalanche cycling indicates that interface trap generation may not be an active degradation mechanism. The impact of the cell pitch on avalanche ruggedness is also investigated by testing 2.5- and 4- m cell-pitch 30-V rated MOSFETs. Measurements showed that the power-law prefactor reduced by 40% when the cell pitch was reduced by 37.5%. The improved VGSTX stability with the smaller cell-pitch MOSFETs is attributed to a lower avalanche current per unit cell resulting in less hot-hole injection and, hence, smaller VGSTX shift. The 2.5-m cell-pitch MOSFETs also show 25% improved on -state resistance RDSON, better RDSON stability, and 20% less subthreshold slope compared with the 4-m cell-pitch MOSFETs, although with 100% higher initial IDSS and less IDSS stability with avalanche cycling. These results are important for manufacturers of automotive MOSFETs where multiple avalanche occurrences over the lifetime of the MOSFET are expected

Aniline effect on concrete steel rebar degradation in saline and sulfate media

Electrochemical potential monitoring experiments were performed on mild steel rebars embedded in concrete admixed with aniline inhibitor and fixed amount of sodium chloride salt partially immersed in sulfuric acid and sodium chloride solution. The open circuit potential corrosion monitoring technique was employed and potential readings were taken in accordance with ASTM C 876. Repressive attribute and consistency of the inhibitor was then estimated by the Weibull probability density distribution as an extreme value statistical modeling approach to study performance effectiveness and predict the most efficient inhibitor concentration in each media. Aniline effect on the compressive strengths of the reinforced concrete samples was also investigated and reported. Varying concentrations of the inhibitor were used and its performance improved as concentration changed in NaCl medium, while no particular order of performance was noted in sulfuric medium. In the statistically analyzed experimental results for each of the inhibitor concentrations employed, 0.34 and 0.41 M aniline admixed samples are identified as exhibiting the best inhibiting quality in sodium chloride while 0.14 M aniline was predicted as showing the lowest probability of corrosion risk in sulfuric acid medium. The overall effective inhibitive performance in sulfuric acid was less when compared to the sodium chloride medium. Concrete sample admixed with 0.41 M aniline had the highest improvement in compressive strength in both media

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions

SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in micro-processor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort

Validation of a software dependability tool via fault injection experiments

Presents the validation of the strategies employed in the RECCO tool to analyze a C/C++ software; the RECCO compiler scans C/C++ source code to extract information about the significance of the variables that populate the program and the code structure itself. Experimental results gathered on an Open Source Router are used to compare and correlate two sets of critical variables, one obtained by fault injection experiments, and the other applying the RECCO tool, respectively. Then the two sets are analyzed, compared, and correlated to prove the effectiveness of RECCO's methodology

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio