Parametric Macromodels of Differential Drivers with Pre-Emphasis

This paper discusses the extraction of behavioral models of differential drivers with pre-emphasis for the assessment of signal integrity and electromagnetic compatibility effects in multigigabit data transmission systems. A suitable model structure is derived and the procedure for its estimation from port transient waveforms is illustrated. The proposed methodology is an extension of the macromodeling based on parametric relations applied to plain differential drivers. The obtained models preserve the accuracy and efficiency strengths of behavioral parametric macromodels for conventional devices. A realistic application example involving a high-speed communication path and a 3.125 Gb/s commercial driver model with pre-emphasis is presente

Modeling and Optimization of the Microwave PCB Interconnects Using Macromodel Techniques

L'abstract è presente nell'allegato / the abstract is in the attachmen

Towards fully automated high-dimensional parameterized macromodeling

This paper presents a fully automated algorithm for the extraction of parameterized macromodels from frequency responses. The reference framework is based on a frequency-domain rational approximation combined with a parameter-space expansion into Gaussian Radial Basis Functions (RBF). An iterative least-squares fitting with positivity constraints is used to optimize model coefficients, with a guarantee of uniform stability over the parameter space. The main novel contribution of this work is a set of algorithms, supported by strong theoretical arguments with associated proofs, for the automated determination of all the hyper-parameters that define model orders, placement and width of RBFs. With respect to standard approaches, which tune these parameters using time-consuming tentative model extractions following a trial-and-error strategy, the presented technique allows much faster tuning of the model structure. The numerical results show that models with up to ten independent parameters are easily extracted in few minutes

Parameterized macromodeling of passive and active dynamical systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

EARLY PERFORMANCE PREDICTION METHODOLOGY FOR MANY-CORES ON CHIP BASED APPLICATIONS

Modern high performance computing applications such as personal computing, gaming, numerical simulations require application-specific integrated circuits (ASICs) that comprises of many cores. Performance for these applications depends mainly on latency of interconnects which transfer data between cores that implement applications by distributing tasks. Time-to-market is a critical consideration while designing ASICs for these applications. Therefore, to reduce design cycle time, predicting system performance accurately at an early stage of design is essential. With process technology in nanometer era, physical phenomena such as crosstalk, reflection on the propagating signal have a direct impact on performance. Incorporating these effects provides a better performance estimate at an early stage. This work presents a methodology for better performance prediction at an early stage of design, achieved by mapping system specification to a circuit-level netlist description. At system-level, to simplify description and for efficient simulation, SystemVerilog descriptions are employed. For modeling system performance at this abstraction, queueing theory based bounded queue models are applied. At the circuit level, behavioral Input/Output Buffer Information Specification (IBIS) models can be used for analyzing effects of these physical phenomena on on-chip signal integrity and hence performance. For behavioral circuit-level performance simulation with IBIS models, a netlist must be described consisting of interacting cores and a communication link. Two new netlists, IBIS-ISS and IBIS-AMI-ISS are introduced for this purpose. The cores are represented by a macromodel automatically generated by a developed tool from IBIS models. The generated IBIS models are employed in the new netlists. Early performance prediction methodology maps a system specification to an instance of these netlists to provide a better performance estimate at an early stage of design. The methodology is scalable in nanometer process technology and can be reused in different designs

Machine Learning Applied to the Blind Identification of Multiple Delays in Distributed Systems

This paper focuses on the application of the Least-Square Support Vector Machine (LS-SVM) regression for the modeling of frequency responses of complex interconnect structures. The goal is to obtain a delayed-rational model (DRM) for the structure accounting for multiple time-delays generated by wave propagation and reflections along the channel. A novel approach for the time-delays estimation based on the LS-SVM regression is introduced. The delays are estimated using the dual space formulation of the LS-SVM with an ad-hoc kernel that considers a possible delay interval. The results highlight the lower order of DRMs obtained using the delays identified through this method when comparing to the vector fitting approach by applying it to a high-speed cable link

Modeling for the Computer-Aided Design of Long Interconnects

L'abstract è presente nell'allegato / the abstract is in the attachmen

Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.Ph.D.Committee Chair: Swaminathan, Madhavan; Committee Member: Fathianathan, Mervyn; Committee Member: Lim, Sung Kyu; Committee Member: Peterson, Andrew; Committee Member: Tentzeris, Mano