Design for Manufacturability in Advanced Lithography Technologies

As the technology nodes keep shrinking following Moore\u27s law, lithography becomes increasingly critical to the fabrication of integrated circuits. The 193nm ArF immersion lithography (193i) has been a common technique for manufacturing integrated circuits. However, the 193i with single exposure has finally reached its printability limit at the 28nm technology node. To keep the pace of Moore\u27s law, design for manufacturability (DFM) is demonstrated to be effective and cost-efficient. The concept of DFM is to modify the design of integrated circuits in order to make them more manufacturable. Tremendous efforts have been made for DFM in advanced lithography technologies. In general, the progress can be summarized in four directions. (1) Advanced lithography process by novel patterning techniques and next-generation lithography; (2) High performance lithography simulation approach in mask synthesis; (3) Physical design (PD) methodology with lithography manufacturability awareness; (4) Robust design flow integrating emerging PD challenges. Accordingly, we propose our research topics in those directions. (1) Throughput optimization for self-aligned double patterning (SADP) and e-beam lithography based manufacturing of 1D layout; (2) Design of efficient rasterization algorithm for mask patterns in inverse lithography technology (ILT); (3) SADP-aware detailed routing; (4) SADP-aware detailed routing with consideration of double via insertion and via manufacturability; (5) Pin accessibility driven detailed placement refinement. In our first research work, we investigate throughput optimization of 1D layout manufacturing. SADP is a mature lithography technique to print 1D gridded layout for advanced technologies. However, in 16nm technology node, trim mask pattern in SADP lithography process may not be printable using 193i along within a single exposure. A viable solution is to complement SADP with e-beam lithography. To order to increase the throughput of 1D layout manufacturing, we consider the problem of e-beam shot minimization subject to bounded line-end extension constraints. Two different approaches of utilizing the trim mask and e-beam to print a 1D layout are considered. The first approach is trimming by end cutting, in which trim mask and e-beam are used to chop up parallel lines at required locations by small fixed rectangles. The second approach is trimming by gap removal, in which trim mask and e-beam are used to rid of all unnecessary portions. We propose elegant integer linear program formulations for both approaches. Experimental results show that both integer linear program formulations can be solved efficiently and have a major speedup compared with previous related work. Furthermore, the pros and cons of the two approaches for manufacturing 1D layout are discussed. In our second research work, we focus on a critical problem of lithography simulation in the design of ILT mask. To reduce the complexity of modern lithography simulation, a widely used approach is to first rasterize the ILT mask before it is inputted to the simulation tool. Accordingly, we propose a high performance rasterization algorithm. The algorithm is based on a pre-computed look-up table. Every pixel in the rasterized image is firstly identified its category: exception or non-exception. Then convolution for every pixel can be performed by a single or multiple look-up table queries depending on its category. In addition, the proposed algorithm has shift invariant property and can be applied for all-angle mask patterns in ILT. Experimental results demonstrate that our approach can speedup conventional rasterization process by almost 500x while maintaining small variations in critical dimension. In our third research work, we concentrate on SADP-aware detailed routing. SADP is a promising manufacturing option for sub-22nm technology nodes due to its good overlay control. To ensure layout is manufacturable by SADP, it is necessary to consider it during layout configuration, e.g., detailed routing stage. However, SADP process is not intuitive in terms of mask design, and considering it during detailed routing stage is even more challenging. We investigate both of two popular types of SADP: spacer-is-dielectric and spacer-is-metal. Different from previous works, we apply the color pre-assignment idea and propose an elegant graph model which captures both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules during detailed routing. A negotiated congestion based rip-up and reroute scheme is applied to achieve good routability while maintaining SADP design rules. Our approach can be extended to consider other multiple patterning lithography during detailed routing, e.g., self-aligned quadruple patterning targeted at sub-10nm technology nodes. Compared with state-of-the-art academic SADP-aware detailed routers, we offer routing solution with better quality of result. In our fourth research work, we extend our SADP-aware detailed routing to consider other manufacturing issues. Both SADP and triple patterning lithography (TPL) are potential layout manufacturing techniques in 10nm technology node. While metal layers can be printed by SADP, via layer manufacturing requires TPL. Previous works on SADP-aware detailed routing do not automatically guarantee via layer are manufacturable by TPL. We extend our SADP-aware detailed routing to consider TPL manufacturability of via layer. Double via insertion is an effective method to improve yield and reliability in integrated circuits manufacturing. We also consider it in our SADP-aware detailed routing to further improve insertion rate. A problem of TPL-aware double via insertion in the post routing stage is proposed. It is solved by both integer linear programming and high-performance heuristic. Experimental results demonstrate that our SADP-aware detailed routing can ensure via layer are TPL manufacturable and improve double via insertion rate. In our last research work, we target at the enhancement of pin access. The significant increased number of routing design rules in advanced technologies has made pin access an emerging difficultly in detailed routing. Resolving pin access in detailed routing may be too late due to the fix pin locations. Thus, we consider pin access in earlier design stage, i.e., detailed placement stage, when perturbation of cell placement is allowed. A cost function is proposed to model pin access for each pin-to-pin connection in detailed routing. A two-phase detailed placement refinement is performed to improve pin access, and refinement techniques are limited to cell flipping, same-row adjacent cell swap and cell shifting. The problem is solved by dynamic programming and linear programming. Experimental results demonstrate that the proposed detailed placement refinement improve pin access and reduce the number of unroutable nets in detailed routing significantly

Standard cell optimization and physical design in advanced technology nodes

Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor technology is IC feature-size miniaturization. However, this brings ever-increasing design complexities and manufacturing challenges to the $340 billion semiconductor industry. The manufacturing of two-dimensional layout on high-density metal layers depends on complex design-for-manufacturing techniques and sophisticated empirical optimizations, which introduces huge amounts of turnaround time and yield loss in advanced technology nodes. Our study reveals that unidirectional layout design can significantly reduce the manufacturing complexities and improve the yield, which is becoming increasingly adopted in semiconductor industry [61, 89]. The lithography printing of unidirectional layout can be tightly controlled using advanced patterning techniques, such as self-aligned double and quadruple patterning. Despite the manufacturing benefits, unidirectional layout leads to more restrictive solution space and brings significant impacts on the IC design automation ow for routing closure. Notably, unidirectional routing limits the standard cell pin accessibility, which further exacerbates the resource competitions during routing. Moreover, for post-routing optimization, traditional redundant-via insertion has become obsolete under unidirectional routing style, which makes the yield enhancement task extremely challenging. Regardless of complex multiple patterning and design-for-manufacturing approaches, mask optimization through resolution enhancement techniques remains as the key strategy to improve the yield of the semiconductor manufacturing processes. Among them, Sub-Resolution Assist Feature (SRAF) generation is a very important method to improve lithographic process windows. Model-based SRAF generation has been widely used to achieve high accuracy but it is time-consuming and hard to obtain consistent SRAFs. This dissertation proposes novel CAD algorithms and methodologies for standard cell optimization and physical design in advanced technology nodes, which ultimately reduces the design cycle and manufacturing cost of IC design. First, a standard cell pin access optimization engine is proposed to evaluate the pin accessibility of a given standard cell library. We further propose novel pin access planning techniques and concurrent pin access optimizations to efficiently resolve the routing resource competitions, which generates much better routing solutions than state-of-the-art, manufacturing-friendly routers. To systematically improve the manufacturing yield in the post-routing stage, a global optimization engine has been introduced for redundant local-loop insertion considering advanced manufacturing constraints. Finally, we propose the first machine learning-based framework for fast yet consistent SRAF generation with the high quality of results.Electrical and Computer Engineerin

EDA Solutions for Double Patterning Lithography

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

DSA-aware multiple patterning for the manufacturing of vias: Connections to graph coloring problems, IP formulations, and numerical experiments

In this paper, we investigate the manufacturing of vias in integrated circuits with a new technology combining lithography and Directed Self Assembly (DSA). Optimizing the production time and costs in this new process entails minimizing the number of lithography steps, which constitutes a generalization of graph coloring. We develop integer programming formulations for several variants of interest in the industry, and then study the computational performance of our formulations on true industrial instances. We show that the best integer programming formulation achieves good computational performance, and indicate potential directions to further speed-up computational time and develop exact approaches feasible for production

Mu Transposon Insertion Sites and Meiotic Recombination Events Co-Localize with Epigenetic Marks for Open Chromatin across the Maize Genome

The Mu transposon system of maize is highly active, with each of the ∼50–100 copies transposing on average once each generation. The approximately one dozen distinct Mu transposons contain highly similar ∼215 bp terminal inverted repeats (TIRs) and generate 9-bp target site duplications (TSDs) upon insertion. Using a novel genome walking strategy that uses these conserved TIRs as primer binding sites, Mu insertion sites were amplified from Mu stocks and sequenced via 454 technology. 94% of ∼965,000 reads carried Mu TIRs, demonstrating the specificity of this strategy. Among these TIRs, 21 novel Mu TIRs were discovered, revealing additional complexity of the Mu transposon system. The distribution of >40,000 non-redundant Mu insertion sites was strikingly non-uniform, such that rates increased in proportion to distance from the centromere. An identified putative Mu transposase binding consensus site does not explain this non-uniformity. An integrated genetic map containing more than 10,000 genetic markers was constructed and aligned to the sequence of the maize reference genome. Recombination rates (cM/Mb) are also strikingly non-uniform, with rates increasing in proportion to distance from the centromere. Mu insertion site frequencies are strongly correlated with recombination rates. Gene density does not fully explain the chromosomal distribution of Mu insertion and recombination sites, because pronounced preferences for the distal portion of chromosome are still observed even after accounting for gene density. The similarity of the distributions of Mu insertions and meiotic recombination sites suggests that common features, such as chromatin structure, are involved in site selection for both Mu insertion and meiotic recombination. The finding that Mu insertions and meiotic recombination sites both concentrate in genomic regions marked with epigenetic marks of open chromatin provides support for the hypothesis that open chromatin enhances rates of both Mu insertion and meiotic recombination

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

Low cost fabrication processing for microwave and millimetre-wave passive components

Microwave and millimetre-wave technology has enabled many commercial applications to play a key role in the development of wireless communication. When dissipative attenuation is a critical factor, metal-pipe waveguides are essential in the development of microwave and millimetre-wave systems. However, their cost and weight may represent a limitation for their application. In the first part of this work two 3D printing technologies and electroless plating were employed to fabricate metal pipe rectangular waveguides in X and W-band. The performance for the fabricated waveguides was comparable to the one of commercially available equivalents, showing good impedance matching and low attenuation losses. Using these technologies, a high-performance inductive iris filter in W-band and a dielectric flap phase shifter in X-band were fabricated. Eventually the design and fabrication of a phased antenna array is reported. For microwave and millimetre-wave applications, system-on-substrate technology can be considered a very valuable alternative, where bulky coax and waveguide interconnects are replaced by low-loss transmission lines embedded into a multilayer substrate, which can include a wide range of components and subsystems. In the second part of this work the integration of RF MEMS with LTCC fabrication process is investigated. Three approaches to the manufacture of suspended structures were considered, based on laser micromachining, laser bending of aluminium foil and hybrid thick/thin film technology. Although the fabrication process posed many challenges, resulting in very poor yield, two of the solution investigated showed potential for the fabrication of low-cost RF MEMS fully integrated in LTCC technology. With the experience gained with laser machining, the rapid prototyping of high aspect ratio beams for silicon MEMS was also investigated. In the third part of this work, a statistical study based on the Taguchi design of experiment and analysis of variance was undertaken. The results show a performance comparable with standard cleanroom processing, but at a fraction of the processing costs and greater design flexibility, due to the lack of need for masks.Open Acces

Regulation of Early Zebrafish Embryogenesis by Calcium Signaling and Dachsous1b Cadherin

Early animal embryogenesis entails a dynamic combination of embryonic cleavages, axial patterning, and gastrulation movements to shape a basic body plan. The underlying molecular signaling responsible for regulating this process remains poorly understood. In this thesis work, I first review recent progress in understanding of gastrulation movements in various model organisms brought by advances in imaging techniques. The externally developing and optically translucent zebrafish embryo is an ideal model organism to study vertebrate embryonic development by in vivo imaging. The objective of my thesis research is to leverage experimental advantages in the zebrafish model to uncover novel regulators and elucidate the molecular mechanisms involved in early vertebrate embryogenesis. Calcium signaling has been implicated in the control of many aspects of embryonic development. However, the spatiotemporal dynamics of calcium signaling during embryogenesis are not well characterized. By generating stable transgenic zebrafish lines ubiquitously expressing GCaMP6s, a genetically encoded calcium indicator, I demonstrated higher activities of calcium signaling during cleavage and blastula stages compared to previous reports. In addition, I showed that superficial dorsal-biased calcium signaling during blastula and gastrula stages was strongly correlated with and dependent on the dorsal organizer establishment. In the developing gastrulae, I directly visualized calcium activity in the dorsal forerunner cells and showed it was modulated by Nodal signaling in a cell non-autonomous manner. The GCaMP6s transgenic lines revealed with unprecedented spatiotemporal resolution the dynamic calcium signaling during early zebrafish embryogenesis and provide a superior tool for future studies. In zebrafish, mutations in atypical cadherin dachsous1b/dchs1b cause pleiotropic embryonic defects, including abnormal cleavages. Using the GCaMP6s transgenic reporter to examine the furrow-associated calcium activity in zebrafish dchs1b mutants, I showed that abnormal cleavages in dchs1b mutants were due to furrow progression defects during cytokinesis. These defects were likely caused by misregulated microtubules, as in vivo imaging of fluorescently marked microtubules during cleavage stages revealed reduced microtubule dynamics and impaired midzone microtubule assembly in dchs1b mutants. I further identified Ttc28 cytoplasmic protein as a molecular link between Dchs1b and microtubule dynamics. My biochemical experiments revealed that Dchs1b physically interacts via its intracellular domain with the tetratricopeptide repeat domain of Ttc28, and controls its subcellular distribution. Moreover, genetic inactivation of ttc28 resulted in increased microtubule dynamics and suppressed the microtubule defects in dchs1b mutants, suggesting a mechanism through which Dchs1b controls embryonic cleavages. In the last part of my thesis, I aimed to determine whether the chemokine ligand Ccl19.a1, a potential upstream regulator of calcium signaling, is required for axial patterning in zebrafish. I demonstrated that TALEN-generated ccl19a.1 mutations produce mildly dorsalized phenotypes and partially suppress the ventralized ichabod/ctnnb2 mutant phenotypes to influence axis formation, providing a genetic evidence for Ccl19.1 acting as a negative regulator of β-catenin and axis formation. Together, my work make several advances in understanding early vertebrate embryogenesis: it characterizes dynamic calcium signaling during zebrafish embryogenesis with a superior spatiotemporal resolution, reveals that Dchs1b regulates microtubule dynamics and embryonic cleavages by interacting with Ttc28 and regulating its subcellular distribution, and provides genetic evidence that Ccl19a.1 is necessary to limit β-catenin activity and consequently axis formation in zebrafish