Fiber link design considerations for cloud-Radio Access Networks

Analog radio over fiber (RoF) links may offer advantages for cloud-Radio Access Networks in terms of component cost, but the behavior of the distortion with large numbers of subcarriers needs to be understood. In this paper, this is presented in terms of the variation between subcarriers. Memory polynomial predistortion is also shown to compensate for RoF and wireless path distortion. Whether for digitized or analog links, it is shown that appropriate framing structure parameters must be used to assure performance, especially of time-division duplex systems

Behavioral modeling and FPGA implementation of digital predistortion for RF and microwave power amplifiers

With the high interest in digital modulation techniques which are very sensitive to the PA nonlinearity, modern wireless communication systems require the usage of linearization techniques to improve the linear behavior of the RF power amplifier. The powerful and cheap digital processing technology makes the digital predistortion (DPD) a competitive candidate for the linearization of the PA. This thesis introduces the basic principle of DPD, its implementation on FPGA and the adaptive DPD system. The linearization of 4 PAs with DPD technique has been introduced: for the hybrid class AB PA operating at 2.6 GHz with a WiMAX testing signal, 33.7 dBm average power, 29.6 % drain efficiency, 13 dB ACPR and 9 dB NMSE improvement have been obtained; for the hybrid Doherty PA operating at 3.4 GHz with an I/Q testing signal, 35.0 dBm average power, 36.8 % drain efficiency, 12 dB ACPR and 13 dB NMSE improvement have been obtained; for the MMIC class AB PA operating at 7 GHz with an I/Q testing signal, 29.4 dBm average power, 25.7 % drain efficiency, 12 dB ACPR and 12 dB NMSE improvement have been obtained; for the two-stage PA operating at 24 GHz with an I/Q testing signal, 23.5 dBm average power, more than 14.0 % drain efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The DPD algorithm has been implemented on FPGA with two methods based on LUT and a direct structure with only adders and multipliers. The block RAM on the FPGA board is chosen as the table in the LUT methods. The linearization performance for these three methods is similar. The test PA is the hybrid Doherty PA mentioned above and the test signal is the I/Q signal with 7.4 dB PAPR. 35.1 dBm average power, 36.8 % efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The cost of logic resources for the direct structure method is the largest with 1,172 flip-flops, while the number of flip-flops for the two LUT methods are 263 and 583, respectively. A new adaptive algorithm has been proposed in this thesis for the adaptive DPD system. This new algorithm improves the performance in extracting the model parameters in complex number domain. With the experimental data from a combined class AB PA, the final accuracy of the model extracted by the new algorithm has been improved from -20 dB to about -40 dB and the converge speed is faster

Robust Digital Predistortion in Saturation Region of Power Amplifiers

This paper proposes a digital predistortion (DPD) technique to improve linearization performance when the power amplifier (PA) is driven near the saturation region. The PA is a non-linear device in general, and the nonlinear distortion becomes severer as the output power increases. However, the PA’s power efficiency increases as the PA output power increases. The nonlinearity results in spectral regrowth, which leads to adjacent channel interference, and degrades the transmit signal quality. According to our simulation, the linearization performance of DPD is degraded abruptly when the PA operates in its saturation region. To relieve this problem, we propose an improved DPD technique. The proposed technique performs on/off control of the adaptive algorithm based on the magnitude of the transmitted signal. Specifically, the adaptation normally works for small and medium signals while it stops for large signals. Therefore, harmful coefficient updates by saturated signals can be avoided. A computer simulation shows that the proposed method can improve the linearization performance compared with the conventional DPD method in highly driven PAs

A Digital Predistortion Scheme Exploiting Degrees-of-Freedom for Massive MIMO Systems

The primary source of nonlinear distortion in wireless transmitters is the power amplifier (PA). Conventional digital predistortion (DPD) schemes use high-order polynomials to accurately approximate and compensate for the nonlinearity of the PA. This is not practical for scaling to tens or hundreds of PAs in massive multiple-input multiple-output (MIMO) systems. There is more than one candidate precoding matrix in a massive MIMO system because of the excess degrees-of-freedom (DoFs), and each precoding matrix requires a different DPD polynomial order to compensate for the PA nonlinearity. This paper proposes a low-order DPD method achieved by exploiting massive DoFs of next-generation front ends. We propose a novel indirect learning structure which adapts the channel and PA distortion iteratively by cascading adaptive zero forcing precoding and DPD. Our solution uses a 3rd order polynomial to achieve the same performance as the conventional DPD using an 11th order polynomial for a 100x10 massive MIMO configuration. Experimental results show a 70% reduction in computational complexity, enabling ultra-low latency communications.Comment: IEEE International Conference on Communications 201

Dynamic selection and estimation of the digital predistorter parameters for power amplifier linearization

© © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.Peer ReviewedPostprint (author's final draft

Compact Digital Predistortion for Multi-band and Wide-band RF Transmitters

This thesis is focusing on developing a compact digital predistortion (DPD) system which costs less DPD added power consumptions. It explores a new theory and techniques to relieve the requirement of the number of training samples and the sampling-rate of feedback ADCs in DPD systems. A new theory about the information carried by training samples is introduced. It connects the generalized error of the DPD estimation algorithm with the statistical properties of modulated signals. Secondly, based on the proposed theory, this work introduces a compressed sample selection method to reduce the number of training samples by only selecting the minimal samples which satisfy the foreknown probability information. The number of training samples and complex multiplication operations required for coefficients estimation can be reduced by more than ten times without additional calculation resource. Thirdly, based on the proposed theory, this thesis proves that theoretically a DPD system using memory polynomial based behavioural modes and least-square (LS) based algorithms can be performed with any sampling-rate of feedback samples. The principle, implementation and practical concerns of the undersampling DPD which uses lower sampling-rate ADC are then introduced. Finally, the observation bandwidth of DPD systems can be extended by the proposed multi-rate track-and-hold circuits with the associated algorithm. By addressing several parameters of ADC and corresponding DPD algorithm, multi-GHz observation bandwidth using only a 61.44MHz ADC is achieved, and demonstrated the satisfactory linearization performance of multi-band and continued wideband RF transmitter applications via extensive experimental tests

A Polynomial Digital Pre-Distortion Technique Based on Iterative Architecture

A digital predistortion (DPD) technique based on an iterative adaptation structure is proposed for linearizing power amplifiers (PAs). To obtain proper DPD parameters, a feedback path that converts the PA’s output to a baseband signal is required, and memory is also needed to store the baseband feedback signals. DPD parameters are usually found by an adaptive algorithm by using the transmitted signals and the corresponding feedback signals. However, for the adaptive algorithm to converge to a reliable solution, long feedback samples are required, which increases hardware complexity and cost. Considering that the convergence time of the adaptive algorithm highly depends on the initial condition, we propose a DPD technique that requires relatively shorter feedback samples. Specifically, the proposed DPD iteratively utilizes the short feedback samples in memory while keeping and using the DPD parameters found at the former iteration as the initial condition at the next iteration. Computer simulation shows that the proposed technique performs better than the conventional technique, as the former requires much shorter feedback memory than the latter

Independent digital predistortion parameters estimation using adaptive principal component analysis

©2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents an estimation/adaptation method based on the adaptive principal component analysis (APCA) technique to guarantee the identification of the minimum necessary parameters of a digital predistorter. The proposed estimation/adaptation technique is suitable for online field-programmable gate array or system on chip implementation. By exploiting the orthogonality of the resulting transformed matrix obtained with the APCA technique, it is possible to reduce the number of coefficients to be estimated which, at the same time, has a beneficial regularization effect by preventing ill-conditioning or overfitting problems. Therefore, this identification/adaptation method enhances the robustness of the parameter estimation and simplifies the adaptation by reducing the number of estimated coefficients. Due to the orthogonality of the new basis, these parameters can be estimated independently, thus allowing for scalability. Experimental results will show that it is possible to determine the minimum number of parameters to be estimated in order to meet the targeted linearity levels while ensuring a robust well-conditioned identification. Moreover, the results will show how thanks to the orthogonality property of the new basis functions, the coefficients of the digital predistorter can be estimated independently. This allows to tradeoff the digital predistorter adaptation time versus performance and hardware complexity.Peer ReviewedPostprint (author's final draft

An implementation of the redirected learning architecture for digital pre-distortion

Digital pre-distortion is a digital signal processing technique that\u27s used to linearize the output of various systems. A common application of digital pre-distortion is to linearize microwave power amplifier circuits, because non-linear distortion can lead to inefficient performance and out of band emissions. Since its conception, several different architectures have been developed for digital pre-distortion. There are online architectures, such as the indirect learning architecture, where signal processing is done while the amplifier is running. There are also offline architectures, such as the direct learning architecture and the relatively new redirected learning architecture, where the signal processing is done using previous input and output data from the amplifier to create a pre-distorted signal. The choice of which architecture to use often comes down to a trade off between performance and complexity. However, a common problem exists between these architectures; the complexity of the pre-distortion technique is bound to the complexity of the system\u27s architecture. Most digital pre-distortion systems in use today use Volterra series filters and their derivatives for behavioral modeling or simple look-up tables. The complexity of applying a given behavioral model to an input signal varies little between architectures, so for a given model the question becomes which architecture will yield the greatest performance. Online methods have excellent performance, though the system required to train the models is computationally complex, as the algorithms to implement them require many calculations in a short period of time; whereas offline methods do not require an expensive training system but may not perform as well. For this reason, it is often desirable to use offline methods to save on system costs and engineering time. Most offline digital pre-distortion systems use the direct learning architecture, however newer architectures may be able to outperform the direct learning architecture with a given behavioral model.In this thesis it is shown how the redirected learning architecture was used to mitigate harmonic distortion by about 30~dB more than the indirect learning architecture. The direct, indirect, and redirected learning architectures are presented, as well as various behavioral models. This is followed by an analysis of the redirected learning architecture. Finally an implementation of the redirected learning model is presented using ADS-Matlab co-simulation. The results are then discussed to show the potential of the redirected learning method