Pipelining of register transfer netlists

This paper describes a method for pipelining of register-to-register netlists. We define algorithms for inserting latches in a data path, both inside each unit and between the units as well as between control logic and the data path and for readjusting the state transition table. Experimental results on several benchmarks show 30%-40% improvement in performance

G0^0 Electronics and Data Acquisition (Forward-Angle Measurements)

The G$^0$ parity-violation experiment at Jefferson Lab (Newport News, VA) is designed to determine the contribution of strange/anti-strange quark pairs to the intrinsic properties of the proton. In the forward-angle part of the experiment, the asymmetry in the cross section was measured for $\vec{e}p$ elastic scattering by counting the recoil protons corresponding to the two beam-helicity states. Due to the high accuracy required on the asymmetry, the G$^0$ experiment was based on a custom experimental setup with its own associated electronics and data acquisition (DAQ) system. Highly specialized time-encoding electronics provided time-of-flight spectra for each detector for each helicity state. More conventional electronics was used for monitoring (mainly FastBus). The time-encoding electronics and the DAQ system have been designed to handle events at a mean rate of 2 MHz per detector with low deadtime and to minimize helicity-correlated systematic errors. In this paper, we outline the general architecture and the main features of the electronics and the DAQ system dedicated to G$^0$ forward-angle measurements.Comment: 35 pages. 17 figures. This article is to be submitted to NIM section A. It has been written with Latex using \documentclass{elsart}. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment In Press (2007

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

One way Doppler extractor. Volume 1: Vernier technique

A feasibility analysis, trade-offs, and implementation for a One Way Doppler Extraction system are discussed. A Doppler error analysis shows that quantization error is a primary source of Doppler measurement error. Several competing extraction techniques are compared and a Vernier technique is developed which obtains high Doppler resolution with low speed logic. Parameter trade-offs and sensitivities for the Vernier technique are analyzed, leading to a hardware design configuration. A detailed design, operation, and performance evaluation of the resulting breadboard model is presented which verifies the theoretical performance predictions. Performance tests have verified that the breadboard is capable of extracting Doppler, on an S-band signal, to an accuracy of less than 0.02 Hertz for a one second averaging period. This corresponds to a range rate error of no more than 3 millimeters per second

Automatic oscillator frequency control system

A frequency control system makes an initial correction of the frequency of its own timing circuit after comparison against a frequency of known accuracy and then sequentially checks and corrects the frequencies of several voltage controlled local oscillator circuits. The timing circuit initiates the machine cycles of a central processing unit which applies a frequency index to an input register in a modulo-sum frequency divider stage and enables a multiplexer to clock an accumulator register in the divider stage with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit compares the remainder held as the contents of the accumulator against a stored zero error constant and applies an appropriate correction word to a correction stage to shift the frequency of the oscillator being checked. A signal from the accumulator register may be used to drive a phase plane ROM and, with periodic shifts in the applied frequency index, to provide frequency shift keying of the resultant output signal. Interposition of a phase adder between the accumulator register and phase plane ROM permits phase shift keying of the output signal by periodic variation in the value of a phase index applied to one input of the phase adder

MIDAS, prototype Multivariate Interactive Digital Analysis System for large area earth resources surveys. Volume 1: System description

A third-generation, fast, low cost, multispectral recognition system (MIDAS) able to keep pace with the large quantity and high rates of data acquisition from large regions with present and projected sensots is described. The program can process a complete ERTS frame in forty seconds and provide a color map of sixteen constituent categories in a few minutes. A principle objective of the MIDAS program is to provide a system well interfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughput. The hardware and software generated in the overall program is described. The system contains a midi-computer to control the various high speed processing elements in the data path, a preprocessor to condition data, and a classifier which implements an all digital prototype multivariate Gaussian maximum likelihood or a Bayesian decision algorithm. Sufficient software was developed to perform signature extraction, control the preprocessor, compute classifier coefficients, control the classifier operation, operate the color display and printer, and diagnose operation

Area Efficient Design of Shift Register through Comparative Analysis of Latches and Flip-Flops

This work presents a energy and area-efficient shift register using pulsed latches. Energy consumption plays an important role in digital systems, because of the requirement to dissipate this energy in high-density circuits and the battery life need to be extended in portable systems such as devices with wireless communication capabilities. Flip-flops consume more energy in digital circuits. In flip flops timing problem occurs due to the redundancy, when the input and the output are in the same state. Several low-power techniques are available but all of them incur transistor-count penalties, leading to an increase in size. In this work the power and energy efficiency of several CMOS master–slave flip-flops and latches are designed and investigated. Among the flip-flops and latches compared, the proposed SSASPL (Static Sense Amplifier with Shared Pulse Generator) circuit is found to be the best energy and area efficient and this circuit is used to design a shift register. This method solves the timing problem through the use of multiple non-overlap delayed pulsed clock signals instead of single pulsed clock signal. The shift register designed by grouping the latches to several sub shift registers and using additional temporary storage latches but uses a small number of the pulsed clock signals. A 16-bit shift register using pulsed latches was fabricated using a 0.18 µm CMOS process with VDD = 1.8v. The proposed shift register saves 52% area and 44% power compared to the conventional shift register with flip-flops

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort

Electronic filters, repeated signal charge conversion apparatus, hearing aids and methods

An electronic filter for filtering an electrical signal. Signal processing circuitry therein includes a logarithmic filter having a series of filter stages with inputs and outputs in cascade and respective circuits associated with the filter stages for storing electrical representations of filter parameters. The filter stages include circuits for respectively adding the electrical representations of the filter parameters to the electrical signal to be filtered thereby producing a set of filter sum signals. At least one of the filter stages includes circuitry for producing a filter signal in substantially logarithmic form at its output by combining a filter sum signal for that filter stage with a signal from an output of another filter stage. The signal processing circuitry produces an intermediate output signal, and a multiplexer connected to the signal processing circuit multiplexes the intermediate output signal with the electrical signal to be filtered so that the logarithmic filter operates as both a logarithmic prefilter and a logarithmic postfilter. Other electronic filters, signal conversion apparatus, electroacoustic systems, hearing aids and methods are also disclosed