114 research outputs found
Emerging physical unclonable functions with nanotechnology
Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs
Reconfigurable horizontal-vertical carrier transport in graphene/HfZrO field-effect transistors
We have fabricated at wafer level field-effect-transistors (FETs) having as channel graphene monolayers transferred on a HfZrO ferroelectric, grown by atomic layer deposition on a doped Si (100) substrate. These FETs display either horizontal or vertical carrier transport behavior, depending on the applied gate polarity. In one polarity, the FETs behave as a graphene FET where the transport is horizontal between two contacts (drain and grounded source) and is modulated by a back-gate. Changing the polarity, the transport is vertical between the drain and the back-gate and, irrespective of the metallic contact type, Ti/Au or Cr/Au, the source-drain bias modulates the height of the potential barrier between HfZrO and the doped Si substrate, the carrier transport being described by a Schottky mechanism at high gate voltages and by a space-charge limited mechanism low gate voltages. Vertical transport is required by three-dimensional integration technologies for increasing the density of transistors on chip
Fault tolerance issues in nanoelectronics
The astonishing success story of microelectronics cannot go on indefinitely. In fact, once
devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected
to impair their behaviour. Fault tolerant techniques will then be required. The aim of this
thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient
error rates for a selection of nanoelectronic gates, based upon quantum cellular automata
and single electron devices, in which the electrostatic interaction between electrons is used
to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant
solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional
techniques are found to be unsuitable. A new technique, in which the voting approach of
triple modular redundancy (TMR) is extended by cascading TMR units composed of
nanogate clusters, is proposed and generalised to other voting approaches. For memory
chips, an error correcting code approach is found to be suitable. Various codes are
considered and a lookup table approach is proposed for encoding and decoding. We are
then able to give estimations for the redundancy level to be provided on nanochips, so as to
make their mean time between failures acceptable. It is found that, for logic chips, space
redundancies up to a few tens are required, if mean times between failures have to be of the
order of a few years. Space redundancy can also be traded for time redundancy. As for
memory chips, mean times between failures of the order of a few years are found to imply
both space and time redundancies of the order of ten
Performance analysis of fault-tolerant nanoelectronic memories
Performance growth in microelectronics, as described by Moore’s law, is steadily
approaching its limits. Nanoscale technologies are increasingly being explored as a
practical solution to sustaining and possibly surpassing current performance trends of
microelectronics. This work presents an in-depth analysis of the impact on performance,
of incorporating reliability schemes into the architecture of a crossbar molecular switch
nanomemory and demultiplexer. Nanoelectronics are currently in their early stages, and
so fabrication and design methodologies are still in the process of being studied and
developed. The building blocks of nanotechnology are fabricated using bottom-up
processes, which leave them highly susceptible to defects. Hence, it is very important that
defect and fault-tolerant schemes be incorporated into the design of nanotechnology
related devices.
In this dissertation, we focus on the study of a novel and promising class of
computer chip memories called crossbar molecular switch memories and their
demultiplexer addressing units. A major part of this work was the design of a defect and
fault tolerance scheme we called the Multi-Switch Junction (MSJ) scheme. The MSJ scheme takes advantage of the regular array geometry of the crossbar nanomemory to
create multiple switches in the fabric of the crossbar nanomemory for the storage of a
single bit.
Implementing defect and fault tolerant schemes come at a performance cost to the
crossbar nanomemory; the challenge becomes achieving a balance between device
reliability and performance. We have studied the reliability induced performance penalties
as they relate to the time (delay) it takes to access a bit, and the amount of power
dissipated by the process. Also, MSJ was compared to the banking and error correction
coding fault tolerant schemes. Studies were also conducted to ascertain the potential
benefits of integrating our MSJ scheme with the banking scheme. Trade-off analysis
between access time delay, power dissipation and reliability is outlined and presented in
this work.
Results show the MSJ scheme increases the reliability of the crossbar
nanomemory and demultiplexer. Simulation results also indicated that MSJ works very
well for smaller nanomemory array sizes, with reliabilities of 100% for molecular switch
failure rates in the 10% or less range
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Modulated Nanowire Structures for Exploring New Nanoprocessor Architectures and Approaches to Biosensing
For the last decade, semiconducting nanowires synthesized by bottom-up methods have opened up new opportunities, stimulated innovative scientific research, and led to applications in materials science, electronics, optics, and biology at the nanoscale. Notably, nanowire building blocks with precise control of size, structure, morphology, and even composition in one, two, and three dimensions can successfully demonstrate high-performance electrical characteristics of field-effect transistors (FETs) and highly sensitive, selective, label-free, real-time biosensors in the fields of nanoelectronics and nano-biosensing, respectively. This thesis has focused on the design, synthesis, assembly, fabrication and electrical characterization of nanowire heterostructures for a proof-of-concept nanoprocessor and morphology-modulated kinked nanowire molecular nanosensor.Physic
Emerging physical unclonable functions with nanotechnology
Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs
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