BioScript: programming safe chemistry on laboratories-on-a-chip

This paper introduces BioScript, a domain-specific language (DSL) for programmable biochemistry which executes on emerging microfluidic platforms. The goal of this research is to provide a simple, intuitive, and type-safe DSL that is accessible to life science practitioners. The novel feature of the language is its syntax, which aims to optimize human readability; the technical contributions of the paper include the BioScript type system and relevant portions of its compiler. The type system ensures that certain types of errors, specific to biochemistry, do not occur, including the interaction of chemicals that may be unsafe. The compiler includes novel optimizations that place biochemical operations to execute concurrently on a spatial 2D array platform on the granularity of a control flow graph, as opposed to individual basic blocks. Results are obtained using both a cycle-accurate microfluidic simulator and a software interface to a real-world platform

Run-time management for future MPSoC platforms

In recent years, we are witnessing the dawning of the Multi-Processor Systemon- Chip (MPSoC) era. In essence, this era is triggered by the need to handle more complex applications, while reducing overall cost of embedded (handheld) devices. This cost will mainly be determined by the cost of the hardware platform and the cost of designing applications for that platform. The cost of a hardware platform will partly depend on its production volume. In turn, this means that ??exible, (easily) programmable multi-purpose platforms will exhibit a lower cost. A multi-purpose platform not only requires ??exibility, but should also combine a high performance with a low power consumption. To this end, MPSoC devices integrate computer architectural properties of various computing domains. Just like large-scale parallel and distributed systems, they contain multiple heterogeneous processing elements interconnected by a scalable, network-like structure. This helps in achieving scalable high performance. As in most mobile or portable embedded systems, there is a need for low-power operation and real-time behavior. The cost of designing applications is equally important. Indeed, the actual value of future MPSoC devices is not contained within the embedded multiprocessor IC, but in their capability to provide the user of the device with an amount of services or experiences. So from an application viewpoint, MPSoCs are designed to ef??ciently process multimedia content in applications like video players, video conferencing, 3D gaming, augmented reality, etc. Such applications typically require a lot of processing power and a signi??cant amount of memory. To keep up with ever evolving user needs and with new application standards appearing at a fast pace, MPSoC platforms need to be be easily programmable. Application scalability, i.e. the ability to use just enough platform resources according to the user requirements and with respect to the device capabilities is also an important factor. Hence scalability, ??exibility, real-time behavior, a high performance, a low power consumption and, ??nally, programmability are key components in realizing the success of MPSoC platforms. The run-time manager is logically located between the application layer en the platform layer. It has a crucial role in realizing these MPSoC requirements. As it abstracts the platform hardware, it improves platform programmability. By deciding on resource assignment at run-time and based on the performance requirements of the user, the needs of the application and the capabilities of the platform, it contributes to ??exibility, scalability and to low power operation. As it has an arbiter function between different applications, it enables real-time behavior. This thesis details the key components of such an MPSoC run-time manager and provides a proof-of-concept implementation. These key components include application quality management algorithms linked to MPSoC resource management mechanisms and policies, adapted to the provided MPSoC platform services. First, we describe the role, the responsibilities and the boundary conditions of an MPSoC run-time manager in a generic way. This includes a de??nition of the multiprocessor run-time management design space, a description of the run-time manager design trade-offs and a brief discussion on how these trade-offs affect the key MPSoC requirements. This design space de??nition and the trade-offs are illustrated based on ongoing research and on existing commercial and academic multiprocessor run-time management solutions. Consequently, we introduce a fast and ef??cient resource allocation heuristic that considers FPGA fabric properties such as fragmentation. In addition, this thesis introduces a novel task assignment algorithm for handling soft IP cores denoted as hierarchical con??guration. Hierarchical con??guration managed by the run-time manager enables easier application design and increases the run-time spatial mapping freedom. In turn, this improves the performance of the resource assignment algorithm. Furthermore, we introduce run-time task migration components. We detail a new run-time task migration policy closely coupled to the run-time resource assignment algorithm. In addition to detailing a design-environment supported mechanism that enables moving tasks between an ISP and ??ne-grained recon??gurable hardware, we also propose two novel task migration mechanisms tailored to the Network-on-Chip environment. Finally, we propose a novel mechanism for task migration initiation, based on reusing debug registers in modern embedded microprocessors. We propose a reactive on-chip communication management mechanism. We show that by exploiting an injection rate control mechanism it is possible to provide a communication management system capable of providing a soft (reactive) QoS in a NoC. We introduce a novel, platform independent run-time algorithm to perform quality management, i.e. to select an application quality operating point at run-time based on the user requirements and the available platform resources, as reported by the resource manager. This contribution also proposes a novel way to manage the interaction between the quality manager and the resource manager. In order to have a the realistic, reproducible and ??exible run-time manager testbench with respect to applications with multiple quality levels and implementation tradev offs, we have created an input data generation tool denoted Pareto Surfaces For Free (PSFF). The the PSFF tool is, to the best of our knowledge, the ??rst tool that generates multiple realistic application operating points either based on pro??ling information of a real-life application or based on a designer-controlled random generator. Finally, we provide a proof-of-concept demonstrator that combines these concepts and shows how these mechanisms and policies can operate for real-life situations. In addition, we show that the proposed solutions can be integrated into existing platform operating systems

Holistic Management of Energy Storage System for Electric Vehicles

While electric vehicles (EVs) have recently gained popularity owing to their economic and environmental benefits, they have not yet dominated conventional combustion-engine vehicles in the market. This is due mainly to their short driving range, high cost and/or quick battery performance degradation. One way to mitigate these shortcomings is to optimize the driving range and the degradation rate with a more efficient battery management system (BMS). This dissertation explores how a more efficient BMS can extend EVs' driving range during their warranty periods. Without changing the battery capacity/size, the driving range and the degradation rate can be optimized by adaptively regulating main operational conditions: battery ambient temperature (T), the amount of transferred battery energy, discharge/charge current (I), and the range of operating voltage (min/max V). To this end, we build a real-time adaptive BMS from a cyber-physical system (CPS) perspective. This adaptive BMS calculates target operation conditions (T, I, min/max V) based on: (a) a battery performance model that captures the effects of operational conditions on the degradation rate and the driving range; (b) a real-time battery power predictor; and (c) a temperature and discharge/charge current scheduler to determine target battery operation conditions that guarantee the warranty period and maximize the driving range. Physical components of the CPS actuate battery control knobs to achieve the target operational conditions scheduled by the batteries cyber components of CPS. There are two subcomponents for each condition (T, I): (d) a battery thermal management system and (e) a battery discharge/charge current management system that consists of algorithms and hardware platforms for each sub-system. This dissertation demonstrates that a more efficient real-time BMS can provide EVs with necessary energy for the specified period of time while slowing down performance degradation. Our proposed BMS adjusts temperature and discharge/charge current in real time, considering battery power requirements and behavior patterns, so as to maximize the battery performance for all battery types and drivers. It offers valuable insight into both current and future energy storage systems, providing more adaptability and practicality for various mobile applications such as unmanned aerial vehicles (UAV) and cellular phones with new types of energy storages.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/143920/1/kimsun_1.pd

Program Composition and Optimization: An Introduction

Software composition connects separately defined software artifacts. Such connection may be in program structure (such as inheritance), data flow (such as message passing) and/or control flow (such as function calls or loop control)

A computer-based product classification and component detection for demanufacturing processes

This is an Author's Accepted Manuscript of an article published in International Journal of Computer Integrated Manufacturing, 24(10), 900-914, 2011 [copyright Taylor & Francis], available online at: http://www.tandfonline.com/10.1080/0951192X.2011.579169.The aim of this paper is to propose a novel computer-based product classification, component detection and tracking for demanufacturing and disassembly process. This is achieved by introducing a series of automated and sequential product scanning, component identification, image analysis and sorting – leading to the development of a bill of material (BOM). The produced BOM can then be associated with the relevant disassembly/demanufacture proviso. The proposed integrated image sorting and product classification (ISPC) approach can be considered as a step forward in automation of demanufacturing activities. The ISPC model proposed in this paper utilises and builds on the state-of-the-art technology and current body of research in computer-integrated demanufacturing and remanufacturing (CIDR). An appraisal of the latest research material and the factors that inhibit CIDR methods inpractice are presented. A novel solution for the integration of imaging and material identification techniques toovercome some of the existing shortcomings of automated recycling processes is proposed in this paper. The proposed product scanning and component detection ISPC software consists of four distinct models: the repertory database, the search engine, the product-attributes updater and the image sorting and classification algorithm. The software framework that integrates the four components is presented in this paper. Finally, an overall assessment of applying ISPC at various stages of CIDR processes concludes the article.University of Ibadan MacArthur Foundation Gran

Response-Time Analysis for Non-Preemptive Periodic Moldable Gang Tasks

Gang scheduling has long been adopted by the high-performance computing community as a way to reduce the synchronization overhead between related threads. It allows for several threads to execute in lock steps without suffering from long busy-wait periods or be penalized by large context-switch overheads. When combined with non-preemptive execution, gang scheduling significantly reduces the execution time of threads that work on the same data by decreasing the number of memory transactions required to load or store the data. In this work, we focus on two main types of gang tasks: rigid and moldable. A moldable gang task has a presumed known minimum and maximum number of cores on which it can be executed at runtime, while a rigid gang task always executes on the same number of cores. This work presents the first response-time analysis for non-preemptive moldable gang tasks. Our analysis is based on the notion of schedule abstraction; a new approach for response-time analysis with the promise of high accuracy. Our experiments on periodic rigid gang tasks show that our analysis is 4.9 times more successful in identifying schedulable tasks than the existing utilization-based test for rigid gang tasks.</p