Towards Single-Chip Nano-Systems

Important scientific discoveries are being propelled by the advent of nano-scale sensors that capture weak signals from their environment and pass them to complex instrumentation interface circuits for signal detection and processing. The highlight of this research is to investigate fabrication technologies to integrate such precision equipment with nano-sensors on a single complementary metal oxide semiconductor (CMOS) chip. In this context, several demonstration vehicles are proposed. First, an integration technology suitable for a fully integrated flexible microelectrode array has been proposed. A microelectrode array containing a single temperature sensor has been characterized and the versatility under dry/wet, and relaxed/strained conditions has been verified. On-chip instrumentation amplifier has been utilized to improve the temperature sensitivity of the device. While the flexibility of the array has been confirmed by laminating it on a fixed single cell, future experiments are necessary to confirm application of this device for live cell and tissue measurements. The proposed array can potentially attach itself to the pulsating surface of a single living cell or a network of cells to detect their vital signs

Gallium Nitride Integrated Microsystems for Radio Frequency Applications.

The focus of this work is design, fabrication, and characterization of novel and advanced electro-acoustic devices and integrated micro/nano systems based on Gallium Nitride (GaN). Looking beyond silicon (Si), compound semiconductors, such as GaN have significantly improved the performance of the existing electronic devices, as well as enabled completely novel micro/nano systems. GaN is of particular interest in the “More than Moore” era because it combines the advantages of a wide-band gap semiconductor with strong piezoelectric properties. Popular in optoelectronics, high-power and high-frequency applications, the added piezoelectric feature, extends the research horizons of GaN to diverse scientific and multi-disciplinary fields. In this work, we have incorporated GaN micro-electro-mechanical systems (MEMS) and acoustic resonators to the GaN baseline process and used high electron mobility transistors (HEMTs) to actuate, sense and amplify the acoustic waves based on depletion, piezoelectric, thermal and piezo-resistive mechanisms and achieved resonance frequencies ranging from 100s of MHz up to 10 GHz with frequency×quality factor (f×Q) values as high as 1013. Such high-performance integrated systems can be utilized in radio frequency (RF) and microwave communication and extreme-environment applications.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/135799/1/azadans_1.pd

Field-effect polymer gating of low-dimensionality carbon-based materials

The work focuses on the modification of the transport properties of low-dimensional carbon based materials by tuning their surface charge carrier density (up to values of induced charge exceeding 2·10^14 carriers/cm^2) via electrochemical gating with an innovative polymer electrolyte solution. Main subjects of the study are single- and few-layer graphene systems produced by micro-mechanical exfoliation and by CVD growth respectively. Attempts to modulate the superconducting critical temperature of the graphite intercalated compounds CaC6 are also made. In addition, polymer gating was also studied on highly oriented pyrolytic graphite, for the first time, to study its properties under high charge induction

A study of the device characteristics of a novel body-contact SOI structure.

Lau Wai Kwok.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references.Acknowledgement --- p.ivAbstract --- p.vChapter Chapter 1 --- Introduction --- p.1-1Chapter 1.1 --- Perspective --- p.1-1Chapter 1.2 --- MEDICI - The Simulation Package --- p.1 -2Chapter 1.3 --- Overview --- p.1-3Chapter Chapter 2 --- The Emergence of SOI Devices --- p.2-1Chapter 2.1 --- Introduction --- p.2-1Chapter 2.2 --- Advantages of SOI Devices --- p.2-1Chapter 2.2.1 --- Reliability Improvement --- p.2-2Chapter 2.2.2 --- Total Isolation --- p.2-3Chapter 2.2.3 --- Improved Junction Structure --- p.2-4Chapter 2.2.4 --- Integrated Device Structure --- p.2-5Chapter 2.3 --- Categories of SOI Devices --- p.2-6Chapter 2.3.1 --- Thick Film SOI Devices --- p.2-7Chapter 2.3.2 --- Thin Film SOI Devices --- p.2-8Chapter 2.3.3 --- Medium Film SOI Devices --- p.2-8Chapter 2.4 --- Drawbacks of SOI Devices --- p.2-9Chapter 2.4.1 --- Floating Body Effects --- p.2-9Chapter 2.4.2 --- Parasitic Bipolar Effects --- p.2-11Chapter 2.4.3 --- Cost --- p.2-15Chapter 2.5 --- Manufacturing Methods --- p.2-16Chapter 2.5.1 --- Epitaxy-Based Method --- p.2-16Chapter 2.5.2 --- Recrystallization-Based Method --- p.2-18Chapter 2.5.3 --- Wafer Bonding Based Method --- p.2-19Chapter 2.5.4 --- Oxidation Based Method --- p.2-20Chapter 2.5.5 --- Implantation Based Method --- p.2-22Chapter 2.6 --- Future Trend --- p.2-22Chapter 2.7 --- The Quest for Silicon-On-Nitride Structure --- p.2-23Chapter Chapter 3 --- Description of Body-Contact SOI Structure --- p.3-1Chapter 3.1 --- Introduction --- p.3-1Chapter 3.2 --- Current Status of Body-Contact SOI Structure --- p.3-1Chapter 3.3 --- The Body-Contact SOI Structure to be studied --- p.3-4Chapter 3.4 --- Impact on Device Fabrication --- p.3-7Chapter 3.4.1 --- Fabrication of Conventional Bulk CMOS --- p.3-7Chapter 3.4.2 --- Fabrication of Conventional SOI CMOS --- p.3-8Chapter 3.4.3 --- Fabrication of BC SOI CMOS --- p.3-10Chapter Chapter 4 --- Device Simulations --- p.4-1Chapter 4.1 --- Introduction --- p.4-1Chapter 4.2 --- MEDICI --- p.4-1Chapter 4.2.1 --- Basic Equations --- p.4-2Chapter 4.2.2 --- Solution Methods --- p.4-3Chapter 4.2.3 --- Initial Guess --- p.4-6Chapter 4.2.4 --- Grid Allocations --- p.4-7Chapter 4.2.5 --- Source File --- p.4-8Chapter 4.3 --- Structures for Simulations --- p.4-9Chapter 4.3.1 --- l.2μm NMOS Bulk (LDD) --- p.4-9Chapter 4.3.2 --- 1.2μm SOI(O) NMOS 1000/3500 NBC --- p.4-11Chapter 4.3.3 --- 1.2μm SOI(N) NMOS 1000/3500 NBC --- p.4-12Chapter 4.3.4 --- 1.2μm SOI(O) NMOS 1000/3500 WBC --- p.4-13Chapter 4.3.5 --- 1.2μm SOI(N) NMOS 1000/3500 WBC --- p.4-14Chapter 4.4 --- Summary --- p.4-14Chapter Chapter 5 --- Simulation Results --- p.5-1Chapter 5.1 --- Introduction --- p.5-1Chapter 5.2 --- Comparisons of Different Structures --- p.5-1Chapter 5.2.1 --- Impurity Profiles of Structures --- p.5-2Chapter 5.2.2 --- Body Effect --- p.5-10Chapter 5.2.3 --- Breakdown Voltage and Transistor Current Driving --- p.5-16Chapter 5.2.4 --- Transconductance and Mobility --- p.5-20Chapter 5.2.5 --- Subthreshold Swing --- p.5-23Chapter 5.3 --- Dependence on Key Structure Parameters --- p.5-29Chapter 5.3.1 --- Dependence on Insulator Thickness --- p.5-29Chapter 5.3.2 --- Dependence on Silicon Overlayer Thickness --- p.5-34Chapter 5.3.3 --- Dependence on Size of Body-Contact --- p.5-37Chapter 5.4 --- Summary --- p.5-40Chapter Chapter 6 --- Reduction of Latch-up Susceptibility --- p.6-1Chapter 6.1 --- Introduction --- p.6-1Chapter 6.2 --- Construction of a p-channel MOS Transistor --- p.6-2Chapter 6.2.1 --- Threshold Voltage and Body Effect --- p.6-3Chapter 6.2.2 --- I-V Characteristics --- p.6-3Chapter 6.2.3 --- Transconductance --- p.6-5Chapter 6.2.4 --- Subthreshold Swing --- p.6-5Chapter 6.3 --- Mechanism of Latch-up in CMOS --- p.6-6Chapter 6.4 --- Construction of a CMOS Invertor for Simulation --- p.6-10Chapter 6.5 --- Latch-up Susceptibility Dependence --- p.6-16Chapter 6.5.1 --- Dependence on Insulator Thickness --- p.6-16Chapter 6.5.2 --- Dependence on N-well Depth --- p.6-19Chapter 6.5.3 --- Dependence on Transistor Separation --- p.6-22Chapter 6.5.4 --- Dependence on Size of Body-Contact --- p.6-25Chapter 6.6 --- Summary --- p.6-28Chapter Chapter 7 --- Conclusions --- p.7-1Chapter 7.1 --- Summary --- p.7-1Chapter 7.2 --- Recommendation --- p.7-3ReferenceAppendix

Field-effect polymer gating of low-dimensionality carbon-based materials

The work focuses on the modification of the transport properties of low-dimensional carbon based materials by tuning their surface charge carrier density (up to values of induced charge exceeding 2·10^14 carriers/cm^2) via electrochemical gating with an innovative polymer electrolyte solution. Main subjects of the study are single- and few-layer graphene systems produced by micro-mechanical exfoliation and by CVD growth respectively. Attempts to modulate the superconducting critical temperature of the graphite intercalated compounds CaC6 are also made. In addition, polymer gating was also studied on highly oriented pyrolytic graphite, for the first time, to study its properties under high charge induction

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

Gated lateral silicon p-i-n junction photodiodes

Research in silicon photonics has recently seen a significant push to develop complete silicon-based optical components for optical communications. Silicon has shown its potential to overcome the bandwidth limitations of microprocessor interconnect, whereas, the silicon platform has already displayed the benefits of low manufacturing costs and CMOS compatibility. The work on “gated lateral silicon p-i-n junction photodiodes” has demonstrated the silicon potential, to detect optical radiations, compatibility to standard CMOS process flow and tuneable spectral response. The lateral structure of gated p-i-n junction photodiodes contributes to high responsivity to short wavelength radiations in these single and dual gate devices. The final objective of this work was to develop high responsivity, CMOS-compatible silicon photodiodes, where the spectral response can be modulated. The lateral p-i-n junction architecture led to high responsivity values, whereas, the MOS gate structure became the basis for tuneable spectral response. The MOS gate structure, made the devices appear as a transistor to the surrounding circuitry and the gate structure in dual gate devices can be used to modulate the spectral response of the device. Single gate devices showed higher responsivity values and comparatively high blue and ultraviolet (UV) response as compared to conventional photodiodes. Surface depletion region in these devices is utilized by placing a MOS gate structure and by patterning an integrated metal grating to detect polarized light. Single and dual gate devices with two variations were fabricated to characterise the device response. Novel lateral architecture of p-i-n junction photodiodes provides a surface depletion region. It is generally anticipated that photodetectors with surface depletion region might produce higher noise. In these devices the surface depletion region has a lateral continuation of gate dielectric which acts as a passivation layer and thus considerably reduced the noise. Physical device modelling studies were performed to verify the experimentally obtained results, which are provided in the relevant measurement chapters. In these devices the speed of operation is a compromise over the high responsivity, CMOS compatibility and tuneable spectral response

Multiphysics modelling of high-speed optoelectronic devices for silicon photonics platforms

L'abstract è presente nell'allegato / the abstract is in the attachmen

Nanoscale characterisation of dielectrics for advanced materials and electronic devices

PhD ThesisStrained silicon (Si) and silicon-germanium (SiGe) devices have long been recognised for their enhanced mobility and higher on-state current compared with bulk-Si transistors. However, the performance and reliability of dielectrics on strained Si/strained SiGe is usually not same as for bulk-Si. Epitaxial growth of strained Si/SiGe can induce surface roughness. The typical scale of surface roughness is generally higher than bulk-Si and can exceed the device size. Surface roughness has previously been shown to impact the electrical properties of the gate dielectric. Conventional macroscopic characterisation techniques are not capable of studying localised electrical behaviour, and thus prevent an understanding of the influence of large scale surface roughness. However scanning probe microscopy (SPM) techniques are capable of simultaneously imaging material and electrical properties. This thesis focuses on understanding the relationship between substrate induced surface roughness and the electrical performance of the overlying dielectric in high mobility strained Si/SiGe devices. SPM techniques including conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been applied to tensile strained Si and compressively strained SiGe materials and devices, suitable for enhancing electron and hole mobility, respectively. Gate leakage current, interface trap density, breakdown behaviour and dielectric thickness uniformity have been studied at the nanoscale. Data obtained by SPM has been compared with macroscopic electrical data from the same devices and found to be in good agreement. For strained Si devices exhibiting the typical crosshatch morphology, the electrical performance and reliability of the dielectric is strongly influenced by the roughness. Troughs and slopes of the crosshatch morphology lead to degraded gate leakage and trapped charge at the interface compared with peaks on the crosshatch undulations. Tensile strained Si material which does not exhibit the crosshatch undulation exhibits improved uniformity in dielectric properties. Quantitative agreement has been found for leakage at a device-level and nanoscale, when accounting for the tip area. The techniques developed can be used to study individual defects or regions on dielectrics whether grown or deposited (including high-κ) and on different substrates including strained Si on insulator (SSOI), strained Ge on insulator (SGOI), strained Ge, silicon carbide (SiC) and graphene. Strained SiGe samples with Ge content varying from 0 to 65% have also been studied. The increase in leakage and trapped charge density with increasing Ge extracted from SPM data is in good agreement with theory and macroscopic data. The techniques appear to be very sensitive, with SCM analysis detecting other dielectric related defects on a 20% Ge sample and the effects of the 65% Ge later exceeding the critical thickness (increased defects and variability in characteristics). Further applications and work to advance the use of electrical SPM techniques are also discussed. These include anti-reflective coatings, synthetic chrysotile nanotubes and sensitivity studies.Overseas Research Students Awards Scheme (ORSAS), School International Research Scholarship (SIRS), Newcastle University International Postgraduate Scholarship (NUIPS) and the Strained Si/SiGe platform grant