Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

High-speed equalization and transmission in electrical interconnections

The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm × 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10−11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAX® backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10−8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

SiGe based multiple-phase VCO operating for mm-wave frequencies

The ever-increasing demand for higher speed in wireless consumer applications has increased the interest in the unlicensed spectrum of 7 GHz around 60 GHz. The high atmospheric oxygen absorption at 60 GHz and small size of the antennas at this frequency requires the use of integrated phased-array systems to overcome the deficiencies of lossy channels at these frequencies. The phased arrays combine signals from multiple paths to obtain higher receiver sensitivity and directivity. The system thus requires phase-shifted voltage-controlled oscillator (VCO) signals to implement phase shifting in the local-oscillator (LO) path. In this research, the vector sum method to generate various phases of the signal at 60 GHz was investigated for its suitability in phased-array systems. The main focus was on improving the phase noise performance of the VCO. The VCO was implemented using a fully differential common-collector Colpitts oscillator in the cascode configuration, which was found to be the VCO configuration with acceptable phase noise performance and stability in the millimetre-wave range. The research focus was on modelling the phase noise of the VCO, and was performed by identifying the impulse sensitivity function for various noise sources, followed by analysing its effect on the linear time varying (LTV) model of the oscillators. The analysis led to a closed-form expression for the phase noise of the oscillator in terms of process and design parameters. The design was then optimised in terms of identified parameters to attain minimum phase noise. The phase noise expression using LTV theory and SpectreRF simulations reported the same optimum value for the design parameter, of around 0.3 for the capacitor ratio. The simulation results utilising the vector sum phase shifting method to generate multiple phase oscillator signals suggest its suitability in implementing phased-array systems in the millimetre-wave range. The vector sum was realised by generating quadrature signals from the oscillator using hybrid couplers. Variable gain amplifiers (VGAs) based on Gilbert mixer topology were used to combine the in-phase and quadrature phase signals to generate the phase-shifted oscillator signal. The gains of the VGAs were linearised by using a pre-distortion circuit, which was an inverse tanh cell. A fully differential 60 GHz VCO was fabricated using a SiGe process with a fT of 200 GHz. The fabricated integrated circuit (IC) measured at the wafer level had a centre frequency of 52.8 GHz and a tuning range of 7 GHz. It demonstrated a phase noise performance of -98.9 dBc/Hz at 1 MHz offset and a power dissipation of 140 mW, thus providing a VCO figure of merit of 172 dBc/Hz. It delivered a differential output power of 8 dBm and the IC occupied an area of 0.54 mm2, including the bondpads. It was thus concluded that a 10 % design margin for the tuning range is required while using SiGe BiCMOS technology. The simulation results demonstrate that the VCO, along with an active interpolator, provides a range of phase-shifted signals from 0° to 360° in steps of 22.5° for various gain settings of the VGAs. The power dissipation of the active interpolator is around 60 mW and the system could thus be employed in LO path shifting architecture of the phased arrays with increased power consumption.Thesis (PhD)--University of Pretoria, 2013.Electrical, Electronic and Computer Engineeringunrestricte

0.42 THz Transmitter with Dielectric Resonator Array Antenna

Off chip antennas do not occupy the expensive die area, as there is no limitation on their building material, and can be built in any size and shape to match the system requirements, which are all in contrast to on-chip antenna solutions. However, integration of off-chip antennas with Monolithic-Microwave-Integrated Chips (MMIC) and designing a low loss signal transmission from the signal source inside the MMIC to the antenna module is a major challenge and trade off. High resistivity silicon (HRS), is a low cost and extremely low loss material at sub-THz. It has become a prevailing material in fabrication of passive components for THz applications. This work makes use of HRS to build an off-chip Dielectric Resonator Antenna Array Module (DRAAM) to realize a highly efficient transmitter at 420 GHz. This work proposes novel techniques and solutions for design and integration of DRRAM with MMIC as the signal source. A proposed scalable 4×4 antenna structure aligns DRRAM on top of MMIC within 2 μm accuracy through an effortless assembly procedure. DRAAM shows 15.8 dB broadside gain and 0.85 efficiency. DRAs in the DRAAM are differentially excited through aperture coupling. Differential excitation not only inherently provides a mechanism to deliver more power to the antenna, it also removes the additional loss of extra balluns when outputs are differential inside MMIC. In addition, this work proposes a technique to double the radiation power from each DRA. Same radiating mode at 0.42 THz inside every DRA is excited through two separate differential sources. This approach provides an almost loss-less power combining mechanism inside DRA. Two 140_GHz oscillators followed by triplers drive each DRA in the demonstrated 4×4 antenna array. Each oscillator generates 7.2 dBm output power at 140 GHz with -83 dBc/Hz phase noise at 100 KHz and consumes 25 mW of power. An oscillator is followed by a tripler that generates -8 dBm output power at 420 GHz. Oscillator and tripler circuits use a smart layer stack up arrangement for their passive elements where the top metal layer of the die is grounded to comply with the planned integration arrangement. This work shows a novel circuit topology for exciting the antenna element which creates the feed element part of the tuned load for the tripler circuit, therefore eliminates the loss of the transition component, and maximizes the output power delivered to the antenna. The final structure is composed of 32 injection locked oscillators and drives a 4×4 DRAAM achieves 22.8 dBm EIRP

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

Design of a Dual Band Local Positioning System

This work presents a robust dual band local positioning system (LPS) working in the 2.4GHz and 5.8GHz industrial science medical (ISM) bands. Position measurement is based on the frequency-modulated continuous wave (FMCW) radar approach, which uses radio frequency (RF) chirp signals for propagation time and therefore distance measurements. Contrary to state of the art LPS, the presented system uses data from both bands to improve accuracy, precision and robustness. A complete system prototype is designed consisting of base stations and tags encapsulating most of the RF and analogue signal processing in custom integrated circuits. This design approach allows to reduce size and power consumption compared to a hybrid system using off-the-shelf components. Key components are implemented using concepts, which support operation in multiple frequency bands, namely, the receiver consisting of a low noise amplifier (LNA), mixer, frequency synthesizer with a wide band voltage-controlled oscillator (VCO) having broadband chirp generation capabilities and a dual band power amplifier. System imperfections occurring in FMCW radar systems are modelled. Effects neglected in literature such as compression, intermodulation, the influence of automatic gain control, blockers and spurious emissions are modeled. The results are used to derive a specification set for the circuit design. Position estimation from measured distances is done using an enhanced version of the grid search algorithm, which makes use of data from multiple frequency bands. The algorithm is designed to be easily and efficiently implemented in embedded systems. Measurements show a coverage range of the system of at least 245m. Ranging accuracy in an outdoor scenario can be as low as 8.2cm. Comparative dual band position measurements prove an effective outlier filtering in indoor and outdoor scenarios compared to single band results, yielding in a large gain of accuracy. Positioning accuracy in an indoor scenario with an area of 276m² can be improved from 1.27m at 2.4GHz and 1.86m at 5.8GHz to only 0.38m in the dual band case, corresponding to an improvement by at least a factor of 3.3. In a large outdoor scenario of 4.8 km², accuracy improves from 1.88m at 2.4GHz and 5.93m at 5.8GHz to 0.68m with dual band processing, which is a factor of at least 2.8.Die vorliegende Arbeit befasst sich mit dem Entwurf eines robusten lokalen Positionierungssystems (LPS), welches in den lizenzfreien Frequenzbereichen für industrielle, wissenschaftliche und medizinische Zwecke (industrial, scientific, medical, ISM) bei 2,4GHz und 5,8GHz arbeitet. Die Positionsbestimmung beruht auf dem Prinzip des frequenzmodulierten Dauerstrichradars (frequency modulated continuous wave, FMCW-Radar), welches hochfrequente Rampensignale für Laufzeitmessungen und damit Abstandsmessungen benutzt. Im Gegensatz zu aktuellen Arbeiten auf diesem Gebiet benutzt das vorgestellte System Daten aus beiden Frequenzbändern zur Erhöhung der Genauigkeit und Präzision sowie Verbesserung der Robustheit. Ein Prototyp des kompletten Systems bestehend aus Basisstationen und mobilen Stationen wurde entworfen. Fast die gesamte analoge hochfrequente Signalverarbeitungskette wurde als anwendungsspezifische integrierte Schaltung realisiert. Verglichen mit Systemen aus Standardkomponenten erlaubt dieser Ansatz die Miniaturisierung der Systemkomponenten und die Einsparung von Leistung. Schlüsselkomponenten wurden mit Konzepten für mehrbandige oder breitbandige Schaltungen entworfen. Dabei wurden Sender und Empfänger bestehend aus rauscharmem Verstärker, Mischer und Frequenzsynthesizer mit breitbandiger Frequenzrampenfunktion implementiert. Außerdem wurde ein Leistungsverstärker für die gleichzeitige Nutzung der beiden definierten Frequenzbänder entworfen. Um Spezifikationen für den Schaltungsentwurf zu erhalten, wurden in der Fachliteratur vernachlässigte Nichtidealitäten von FMCW-Radarsystemen modelliert. Dazu gehören Signalverzerrungen durch Kompression oder Intermodulation, der Einfluss der automatischen Verstärkungseinstellung sowie schmalbandige Störer und Nebenschwingungen. Die Ergebnisse der Modellierung wurden benutzt, um eine Spezifikation für den Schaltungsentwurf zu erhalten. Die Schätzung der Position aus gemessenen Abständen wurde über eine erweiterte Version des Gittersuchalgorithmus erreicht. Dieser nutzt die Abstandsmessdaten aus beiden Frequenzbändern. Der Algorithmus ist so entworfen, dass er effizient in einem eingebetteten System implementiert werden kann. Messungen zeigen eine maximale Reichweite des Systems von mindestens 245m. Die Genauigkeit von Abstandsmessungen im Freiland beträgt 8,2cm. Positionsmessungen wurden unter Verwendung beider Einzelbänder durchgeführt und mit den Ergebnissen des Zweiband-Gittersuchalgorithmus verglichen. Damit konnte eine starke Verbesserung der Positionsgenauigkeit erreicht werden. Die Genauigkeit in einem Innenraum mit einer Grundfläche von 276m² kann verbessert werden von 1,27m bei 2,4GHz und 1,86m bei 5,8GHz zu nur 0,38m im Zweibandverfahren. Das entspricht einer Verbesserung um einen Faktor von mindestens 3,3. In einem größeren Außenszenario mit einer Fläche von 4,8 km² verbessert sich die Genauigkeit um einen Faktor von mindestens 2,8 von 1,88m bei 2,4GHz und 5,93m bei 5,8GHz auf 0,68m bei Nutzung von Daten aus beiden Frequenzbändern

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%

Schaltungen zur Frequenzumsetzung für drahtlose Übertragungssysteme im Millimeterwellenbereich

Diese Arbeit beschreibt den Entwurf, die Analyse und die Verifikation von integrierten Schaltungen zur Frequenzumsetzung für drahtlose Übertragungssysteme im Millimeterwellenbereich. Bei der Beschreibung der zur Verfügung stehenden Halbleitertechnologien und der Aufbau- und Verbindungstechniken wird deutlich, dass parasitäre Widerstände, Kapazitäten und Induktivitäten sämtlicher Verbindungen Verluste und Reflexionen verursachen, die mit der Signalfrequenz ansteigen. Dies motiviert die Reduktion der Signalfrequenz zur Verringerung dieser Verluste, soweit wie dies in einem Millimeterwellensystem möglich ist. Neben den in drahtlosen Übertragungssystemen ohnehin erforderlichen Mischern zur Modulation und Demodulation werden in dieser Arbeit auch Frequenzmultiplizierer vorgestellt. Mit diesen Schaltungen ist es möglich, das hochfrequente Trägersignal direkt neben den Mischern zu erzeugen und mit möglichst kurzen Leitungen anzuschließen, sodass die parasitären Verluste dieser Verbindung sowie die Reflexionen minimal werden. Mit Ausnahme der Verbindungen zu den Antennen kann dadurch die Frequenz der restlichen extern anzuschließenden Signale, nämlich des zu übertragenden Basisbandsignals und des subharmonischen LO-Signals, wesentlich verringert werden, wodurch die Verluste insgesamt reduziert werden. In dieser Arbeit werden dafür zwei Frequenzverdoppler und ein Frequenzversechsfacher vorgestellt, die jeweils mit einer Eingangsfrequenz im Bereich um 30 GHz Ausgangssignale bei 60 GHz bzw. bei 180 GHz erzeugen. Diese drei Schaltungen wurden mit einem Schwerpunkt auf der Unterdrückung unerwünschter Harmonischer und einer gleichzeitig effizienten Erzeugung der gewünschten Harmonischen entworfen. Damit konnte der Stand der Technik für BiCMOS-Frequenzmultiplizierer mit einer Ausgangsfrequenz von bis zu 210 GHz verbessert werden. Sowohl hinsichtlich der absoluten DC-Leistung des Frequenzversechsfachers von lediglich 63 mW, als auch bezüglich der Effizienz (PAE) von 0,28 %, der Verstärkung von 10 dB und der Unterdrückung unerwünschter Harmonischer von bis zu 35 dB sind die erzielten Ergebnisse außerdem besser als von einigen Schaltungen aus leistungsfähigeren III-V-Halbleiterprozessen. Passend zur Mittenfrequenz von 180 GHz am Ausgang des Frequenzversechsfachers, die auch die Mittenfrequenz des IEEE G-Bands ist, werden außerdem integrierte Aufwärts- und Abwärtsmischer entwickelt, die auf der für Kommunikationssysteme vergleichsweise wenig beachteten Sechstor-Architektur basieren. Die Vorteile der Sechstor-Architektur wurden zuvor bereits bei niedrigeren Frequenzen sowohl mit integrierten als auch mit diskret aufgebauten Schaltungen demonstriert. Ein Ziel dieser Arbeit ist die darauf aufbauende Entwicklung und Untersuchung von integrierten I-Q-Mischern mit dieser Architektur für drahtlose Kommunikationssysteme bei 180 GHz in einem 130 nm-BiCMOS-Prozess. Dafür werden geeignete Detektoren und Reflektoren präsentiert, mit denen die Implementierung in diesem Frequenzbereich möglich ist. Mit den erzielten Ergebnissen konnte jeweils der Stand der Technik für integrierte Sechstor-Aufwärts- und -Abwärtsmischer verbessert werden: Im Fall der Sechstor-Aufwärtsmischer stellen die durchgeführten Messungen die erste Verifikation dieser Architektur im Millimeterwellenbereich dar. Auch im Fall der Abwärtsmischer ist die entworfene Schaltung die erste Realisierung bei einer Mittenfrequenz von über 120 GHz. Die erzielten Ergebnisse zeigen, dass die Sechstor-Architektur im Millimeterwellenbereich für die Anwendung in drahtlosen Übertragungssystemen geeignet ist. Hinsichtlich der HF-Eigenschaften sind die erzielten Ergebnisse vergleichbar mit oder besser als solche, die mit technologisch aufwendigeren und oftmals energieintensiveren Schalter-Mischern, wie z.B. den Gilbert-Mischern, erreicht werden. Darüber hinaus wird anhand von mathematischen Schaltungsanalysen gezeigt, dass sich diese Mischerarchitektur ebenfalls durch ihre gute analytische Modellierbarkeit auszeichnet. Selbst mit stark idealisierten und vereinfachten Modellen kann der Mischgewinn bei 180 GHz mit einer Abweichung zur Messung und zur Simulation von lediglich rund 5 dB berechnet werden.:Kurzfassung Abstract Symbolverzeichnis Vorveröffentlichungen 1. Einleitung 2. Fertigungsprozesse für Schaltungen im Millimeterwellenbereich 2.1. Halbleitertechnologien 2.2. Aufbau- und Verbindungstechnik 2.3. Reduktion von Verlusten mittels Frequenzumsetzung 3. Frequenzmultiplizierer 3.1. Frequenzverdoppler mit Polyphasenfilter 3.2. Frequenzverdoppler mit aktivem und passivem Balun 3.3. Frequenzversechsfacher 3.4. Anwendung in einem Millimeterwellensystem 4. Mischer 4.1. Sechstor-Interferometer 4.2. Sechstor-Abwärtsmischer 4.3. Sechstor-Aufwärtsmischer 5. Zusammenfassung und Ausblick A. Betragsberechnungen der auslaufenden Wellen des Sechstors B. Lösung der nichtlinearen Differenzialgleichung C. Differenzen der Quadrate und Kuben harmonischer Summen Literaturverzeichnis DanksagungIn this thesis the design, analysis and verification of integrated circuits for wireless communication systems operating at millimeter waves is presented. During a review of the available manufacturing processes for integrated circuits, printed circuit boards, and interconnects, problems associated with these techniques are identified. Parasitic elements, such as resistors, capacitors, and inductors introduce losses that increase with the signal frequency. This motivates the reduction of the signal frequency wherever possible, so as to reduce these frequency-dependent losses. To achieve this, millimeterwave up- and downconverting mixers, which are anyway required in wireless systems for the modulation and demodulation of an rf carrier signal, and frequency multipliers for generation of those carrier signals are presented in this thesis. With the frequency multipliers it is possible to generate the carrier signals as spatially close to the mixers as possible, reducing the required length of the connection and the losses and reflecions associated with it. Two frequency doublers and a frequency sixtupler were designed for the conversion of input signals at 30 GHz to output signals at 60 GHz and at 180 GHz, respectively. The designs are focused on an energy-efficient generation of the desired harmonic and a large suppression of other undesired harmonics. In this way, the demonstrated results for the frequency sixtupler at 180 GHz improve the state-of-the-art for both BiCMOS and III-V circuits in terms of power consumption, power added efficiency (PAE), conversion gain and harmonic suppression. With the output frequency at up to 210 GHz and with a dc power consumption of 63 mW, a conversion gain of 10 dB, a PAE of 0.28 %, and a harmonic suppression of 35 dB is reached. Matching the output frequency of the sixtupler, two quadrature mixers operating at 180 GHz are presented. They are based on the six-port technique, which offers some promising features at millimeter wave frequencies, but is still not very popular for the application in integrated communication systems. Some research has already been conducted on six-port receivers for radar and communication systems operating at lower frequencies, both as integrated circuits and on printed circuit boards. In the case of six-port downconversion mixers, competetive results with discrete III-V diodes and transistors on printed circuit boards were demonstrated, but very little research on integrated realizations has been published to date. One goal of this thesis is therefore to design integrated six-port mixers at 180 GHz and investigate this architecture for the quadrature up- and downconversion in communication systems. Suitable active detectors and reflectors are proposed to enable the implementation of the six-port technique at these frequencies. In this way, the first implementation of the six-port technique for the upconversion at millimeterwave frequencies is demonstrated. For the downconversion, the rf center frequency at 180 GHz is the highest among six-port implementations to date. The results in terms of rf performance compare well against state-of-the-art switching mixers, such as Gilbert cells. Moreover, the six-port architecture is found to be much simpler in terms of the circuit complexity and it enables the circuit analysis using only simple and idealistic models. With such models, the conversion gain at 180 GHz can be calculated with an error of only about 5 dB. In its minimal realization, a quadrature mixer with a very low dc power consumption can be designed. This makes the six-port technique increasingly attractive as the rf frequency is increased and switching mixers consume a higher dc and rf power.:Kurzfassung Abstract Symbolverzeichnis Vorveröffentlichungen 1. Einleitung 2. Fertigungsprozesse für Schaltungen im Millimeterwellenbereich 2.1. Halbleitertechnologien 2.2. Aufbau- und Verbindungstechnik 2.3. Reduktion von Verlusten mittels Frequenzumsetzung 3. Frequenzmultiplizierer 3.1. Frequenzverdoppler mit Polyphasenfilter 3.2. Frequenzverdoppler mit aktivem und passivem Balun 3.3. Frequenzversechsfacher 3.4. Anwendung in einem Millimeterwellensystem 4. Mischer 4.1. Sechstor-Interferometer 4.2. Sechstor-Abwärtsmischer 4.3. Sechstor-Aufwärtsmischer 5. Zusammenfassung und Ausblick A. Betragsberechnungen der auslaufenden Wellen des Sechstors B. Lösung der nichtlinearen Differenzialgleichung C. Differenzen der Quadrate und Kuben harmonischer Summen Literaturverzeichnis Danksagun