Transforming timing diagrams into knowledge acquisition in automated specification

Requirements engineering is an important part of developing programs. It is an essential stage of the software development process that defines what a product or system should to achieve. The UML Timing diagram and Knowledge Acquisition in Automated Specification (KAOS) model are requirements engineering techniques. KAOS is a goal-oriented requirements approach while the Timing diagram is a graphical notation used for explaining software timing requirements. KAOS uses linear temporal logic (LTL) to describe time constraints in goal and operation models. Similarly, the Timing diagram can describe some temporal operators such as X (next), U (until) and R (release) over some period of time. Thus, our aim is to use the Timing diagram to generate parts of a KAOS model. In this paper we demonstrate techniques for creating a KAOS goal model from a Timing diagram. The Timing diagram which is used in this paper is adapted from the UML 2.0 Timing diagram and includes features to support translation into KAOS. We use a case study of a Lift system as an example to explain the translation processes described here

Fluent temporal logic for discrete-time event-based models

Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-based and state-based formalisms is defined through fluents which are state predicates whose value are determined by the occurrences of initiating and terminating events that make the fluents values become true or false, respectively. The existing fluent temporal logic is convenient for reasoning about untimed event-based models but difficult to use for timed models. The paper extends fluent temporal logic with temporal operators for modelling timed properties of discrete-time event-based models. It presents two approaches that differ on whether the properties model the system state after the occurrence of each event or at a fixed time rate. Model checking of timed properties is made possible by translating them into the existing untimed framework. Copyright 2005 ACM

Runtime validation using interval temporal logic

Formal specifications are one of the design choices in reactive and/or real-time systems as a number of notations exist to formally define parts of the system. However, defining the system formally is not enough to guarantee correctness thus the specifications are used as execution monitors over the system. A number of projects are around that provides a framework to define execution monitors in Interval Temporal Logic (ITL), such as Temporal-Rover, EAGLE Flier, and D3CA framework. This paper briefly describes the D3CA framework, consisting in the adaptation of Quantified Discrete-Time Duration Calculus to monitoring assertions. The D3CA framework uses the synchronous data-flow programming language Lustre as a generic platform for defining the notation. Additionally, Lustre endows the framework with the ability to predetermine the space and time requirements of the monitoring system. After defining the notation framework the second part of the paper presents two case studies - a mine pump and an answering machine. The case studies illustrate the power endowed by using ITL observers in a reactive or event-driven system.peer-reviewe

A timeband framework for modelling real-time systems

Complex real-time systems must integrate physical processes with digital control, human operation and organisational structures. New scientific foundations are required for specifying, designing and implementing these systems. One key challenge is to cope with the wide range of time scales and dynamics inherent in such systems. To exploit the unique properties of time, with the aim of producing more dependable computer-based systems, it is desirable to explicitly identify distinct time bands in which the system is situated. Such a framework enables the temporal properties and associated dynamic behaviour of existing systems to be described and the requirements for new or modified systems to be specified. A system model based on a finite set of distinct time bands is motivated and developed in this paper

Hybrid Genetic Algorithms for Scheduling High-Speed Multimedia Systems

It has been observed that most conventional operating systems could not cope with the scheduling of multimedia tasks owing to the large size of these files. For instance, processing of multimedia tasks using the traditional operating systems are fraught with problems such as low quality of service and delay jitters. In order to address these problems, a scheduling algorithm christened hybrid genetic algorithm for multimedia task scheduling (HGAMTS) was developed. It employed heuristic knowledge of the problem domain to model a hybrid genetic algorithm in a multiprocessor environment. The system is made up of the scheduler model and the task model. The scheduler model consist a centralized dynamic scheduling scheme. In this scheme, all tasks arrive at a central processor (scheduler). The model has a minimum of five and maximum of ten processors. Attached to each processor is a dispatch queue

Ensino de Microcontroladores usando a família MSP430

Este artigo descreve o uso da família de microcontroladores MSP430 nas aulas dos cursos de Engª Electromecânica e Engª Electrotécnica. Esta família de microcontroladores foi escolhida devido às suas características e capacidades. O custo do μC e dos sistemas de desenvolvimento, a disponibilidade de várias ferramentas de desenvolvimento e o grande número de periféricos que esta família de microcontroladores possui permite o desenvolvimento de aplicações com o enfoque desejado para as aulas. As capacidades de análise de erros do software e as ferramentas de programação em linguagem C permitem uma aprendizagem mais acessível por parte dos alunos.Tendo em atenção as principais capacidades que queremos fornecer aos nossos estudantes, neste artigo vamos mostrar algumas das aplicações desenvolvidas e algumas em desenvolvimento pelo grupo de trabalho em microprocessadores do Departamento de Electromecânica da Universidade da Beira Interior. O objectivo deste artigo é o de mostrar uma forma acessível para o ensino de microprocessadores fazendo uso de ferramentas simples, mas ao mesmo tempo, poderosas e completas, que podem ser usadas numa grande variedade de aplicações.info:eu-repo/semantics/publishedVersio