Scalable Architecture of MIMO Multi-carrier CDMA System on Programmable Logic

In this paper, a scalable architecture of the multicarrier CDMA system using Multiple-Input-Multiple-Output (MIMO) technology is designed in the programmable logic array. The system-level partitioning with different architecture design entries is described. The overall computing architecture for complex signal processing blocks, e.g., channel estimation, frequency domain equalization, demodulation etc is described. The MIMO architecture is easily extended from a SISO system with single antenna. This scalable architecture demonstrates resource utilization efficiency and easy extension to MIMO configurations

Application priority framework for fixed mobile converged communication networks

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.The current prospects in wired and wireless access networks, it is becoming increasingly important to address potential convergence in order to offer integrated broadband services. These systems will need to offer higher data transmission capacities and long battery life, which is the catalyst for an everincreasing variety of air interface technologies targeting local area to wide area connectivity. Current integrated industrial networks do not offer application aware context delivery and enhanced services for optimised networks. Application aware services provide value-added functionality to business applications by capturing, integrating, and consolidating intelligence about users and their endpoint devices from various points in the network. This thesis mainly intends to resolve the issues related to ubiquitous application aware service, fair allocation of radio access, reduced energy consumption and improved capacity. A technique that measures and evaluates the data rate demand to reduce application response time and queuing delay for multi radio interfaces is proposed. The technique overcomes the challenges of network integration, requiring no user intervention, saving battery life and selecting the radio access connection for the application requested by the end user. This study is split in two parts. The first contribution identifies some constraints of the services towards the application layer in terms of e.g. data rate and signal strength. The objectives are achieved by application controlled handover (ACH) mechanism in order to maintain acceptable data rate for real-time application services. It also looks into the impact of the radio link on the application and identifies elements and parameters like wireless link quality and handover that will influence the application type. It also identifies some enhanced traditional mechanisms such as distance controlled multihop and mesh topology required in order to support energy efficient multimedia applications. The second contribution unfolds an intelligent application priority assignment mechanism (IAPAM) for medical applications using wireless sensor networks. IAPAM proposes and evaluates a technique based on prioritising multiple virtual queues for the critical nature of medical data to improve instant transmission. Various mobility patterns (directed, controlled and random waypoint) has been investigated and compared by simulating IAPAM enabled mobile BWSN. The following topics have been studied, modelled, simulated and discussed in this thesis: 1. Application Controlled Handover (ACH) for multi radios over fibre 2. Power Controlled Scheme for mesh multi radios over fibre using ACH 3. IAPAM for Biomedical Wireless Sensor Networks (BWSN) and impact of mobility over IAPAM enabled BWSN. Extensive simulation studies are performed to analyze and to evaluate the proposed techniques. Simulation results demonstrate significant improvements in multi radios over fibre performance in terms of application response delay and power consumption by upto 75% and 15 % respectively, reduction in traffic loss by upto 53% and reduction in delay for real time application by more than 25% in some cases

Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies

Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support

Architectures matérielles pour la technologie W-CDMA étendue aux systèmes multi-antennes

Depuis une dizaine d 'années, l'avènement des techniques multi-antennes (ou MIMO) pour les communications sans fil , mobiles ou fixes , a révolutionné les possibilités offertes pour de nombreux domaines d 'application des télécommunications. La disposition de plusieurs antennes de part et d 'autre du lien augmente considérablement la capacité des systèmes sans fil. Cependant, les algorithmes numériques à mettre en oeuvre pour réaliser ces systèmes sont autrement complexes et constituent un challenge quant à la définition d'architectures matérielles performantes. L'objectif du travail présent repose précisément sur la définition optimale de solutions architecturales, dans un contexte CDMA, pour contrer cette problématique. Le premier aspect de ce travail porte sur une étude approfondie des algorithmes spatio-temporels et des méthodes de conception en vue d'une implantation matérielle efficace. De nombreux schémas de détection sont proposés dans la littérature et sont applicables suivant trois critères qui sont: la qualité de service, le débit binaire et la complexité algorithmique. Cette dernière constitue une contrainte forte pour une mise en application à faible coût de terminaux mobiles intégrant ces applications. Aussi, il est nécessaire de disposer d'outils performants pour simuler, évaluer et affiner (prototypage rapide) ces nouveaux systèmes, candidats probables pour les télécommunications de quatrième génération. Le second aspect concerne la réalisation d'un transcepteur multi-antennes sans codage de canal, intégrant la technologie d'accès multiple par répartition de codes dans le cas d'un canal large bande. Un système mono-antenne WCDMA, généralisable à un nombre quelconque d'antennes, a été intégré et simulé au sein de la plate-forme de prototypage rapide Lyrtech. L'architecture développée intègre les principaux modules du traitement en bande de base, à savoir le filtrage de Nyquist, la détection des multiples trajets suivie de l'étape de détection. Le prototype MIMO-WCDMA développé est caractérisé par sa flexibilité suivant le nombre de voies e~trantes, le format d'entrée des échantillons, les caractéristiques du canal sans fil et la technologie ciblée (ASIC, FPGA). Le troisième aspect se veut plus prospectif en détaillant de nouveaux mécanismes pour réduire le coût matériel des systèmes multi-antennes. Le principe d'allocation adaptative de la virgule fixe est présenté dans le but d'adapter le codage des données suivant les caractéristiques du canal sans fil et de minimiser en conséquence la complexité du circuit. D'autre part, le concept d'architectures adaptatives est proposé afin de minimiser l'énergie consommée au sein d 'un système embarqué suivant le contexte d'application

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

Energy-Efficient Decoders of Near-Capacity Channel Codes.

Channel coding has become essential in state-of-the-art communication and storage systems for ensuring reliable transmission and storage of information. Their goal is to achieve high transmission reliability while keeping the transmit energy consumption low by taking advantage of the coding gain provided by these codes. The lowest total system energy is achieved with a decoder that provides both good coding gain and high energy-efficiency. This thesis demonstrates the VLSI implementation of near-capacity channel decoders using the LDPC, nonbinary LDPC (NB-LDPC) and polar codes with an emphasis of reducing the decode energy. LDPC code is a widely used channel code due to its excellent error-correcting performance. However, memory dominates the power of high-throughput LDPC decoders. Therefore, these memories are replaced with a novel non-refresh embedded DRAM (eDRAM) taking advantage of the deterministic memory access pattern and short access window of the decoding algorithm to trade off retention time for faster access speed. The resulting LDPC decoder with integrated eDRAMs achieves state-of-the-art area- and energy-efficiency. NB-LDPC code achieves better error-correcting performance than LDPC code at the cost of higher decoding complexity. However, the factor graph is simplified, permitting a fully parallel architecture with low wiring overhead. To reduce the dynamic power of the decoder, a fine-grained dynamic clock gating technique is applied based on node-level convergence. This technique greatly reduces dynamic power allowing the decoder to achieve high energy-efficiency while achieving high throughput. The recently invented polar code has a similar error-correcting performance to LDPC code of comparable block length. However, the easy reconfigurability of code rate as well as block length makes it desirable in numerous applications where LDPC is not competitive. In addition, the regular structure and simple processing enables a highly efficient decoder in terms of area and power. Using the belief propagation algorithm with architectural and memory improvements, a polar decoder is demonstrated achieving high throughput and high energy- and area-efficiency. The demonstrated energy-efficient decoders have advanced the state-of-the-art. The decoders will allow the continued reduction of decode energy for the latest communication and storage applications. The developed techniques are widely applicable to designing low-power DSP processors.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/108731/1/parkyoun_1.pd

VLSI decoding architectures: flexibility, robustness and performance

Stemming from previous studies on flexible LDPC decoders, this thesis work has been mainly focused on the development of flexible turbo and LDPC decoder designs, and on the narrowing of the power, area and speed gap they might present with respect to dedicated solutions. Additional studies have been carried out within the field of increased code performance and of decoder resiliency to hardware errors. The first chapter regroups several main contributions in the design and implementation of flexible channel decoders. The first part concerns the design of a Network-on-Chip (NoC) serving as an interconnection network for a partially parallel LDPC decoder. A best-fit NoC architecture is designed and a complete multi-standard turbo/LDPC decoder is designed and implemented. Every time the code is changed, the decoder must be reconfigured. A number of variables influence the duration of the reconfiguration process, starting from the involved codes down to decoder design choices. These are taken in account in the flexible decoder designed, and novel traffic reduction and optimization methods are then implemented. In the second chapter a study on the early stopping of iterations for LDPC decoders is presented. The energy expenditure of any LDPC decoder is directly linked to the iterative nature of the decoding algorithm. We propose an innovative multi-standard early stopping criterion for LDPC decoders that observes the evolution of simple metrics and relies on on-the-fly threshold computation. Its effectiveness is evaluated against existing techniques both in terms of saved iterations and, after implementation, in terms of actual energy saving. The third chapter portrays a study on the resilience of LDPC decoders under the effect of memory errors. Given that the purpose of channel decoders is to correct errors, LDPC decoders are intrinsically characterized by a certain degree of resistance to hardware faults. This characteristic, together with the soft nature of the stored values, results in LDPC decoders being affected differently according to the meaning of the wrong bits: ad-hoc error protection techniques, like the Unequal Error Protection devised in this chapter, can consequently be applied to different bits according to their significance. In the fourth chapter the serial concatenation of LDPC and turbo codes is presented. The concatenated FEC targets very high error correction capabilities, joining the performance of turbo codes at low SNR with that of LDPC codes at high SNR, and outperforming both current deep-space FEC schemes and concatenation-based FECs. A unified decoder for the concatenated scheme is subsequently propose