RF Circuit linearity optimization using a general weak nonlinearity model

This paper focuses on optimizing the linearity in known RF circuits, by exploring the circuit design space that is usually available in today’s deep submicron CMOS technologies. Instead of using brute force numerical optimizers we apply a generalized weak nonlinearity model that only involves AC transfer functions to derive simple equations for obtaining design insights. The generalized weak nonlinearity model is applied to three known RF circuits: a cascode common source amplifier, a common gate LNA and a CMOS attenuator. It is shown that in deep submicron CMOS technologies the cascode transistor in both the common source amplifier and in the common gate amplifier significantly contributes IM3 distortion. Some design insights are presented for reducing the cascode transistor related distortion, among which moderate inversion biasing that improves IIP3 by 10 dB up to 5 GHz in a 90 nm CMOS process. For the attenuator, a wideband IM3 cancellation technique is introduced and demonstrated using simulations

Design and analysis techniques for nano-joule ADCs and sampling linearity

Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling network. Low energy analog design techniques for emerging systems powered by energy scavenging are demonstrated in the context of an analog-to-digital converter system. It is composed of a variable gain sample-and-hold amplifier, a low voltage reference, a 1.5 bit per stage 9-b cyclic ADC, clock generation, reference buffers, and control logic. A novel Class-AB current mirror amplifier together with correlated level shifting enable wide swing and enhanced gain operation at low supply voltages while reducing current draw. The use of subthreshold MOSFETs instead of bipolar junction transistors allows the use of traditional bandgap circuit techniques to be employed for a 530 mV reference that is less than a diode voltage drop. Operating from a 750 mV supply voltage and 20.48 kSPS, the ADC and reference consume 9.5μA and 1.5μA, respectively. The measured 7.9-bit ENOB results in an FoM of 2.24 pJ/step. The total energy consumption is 535 pJ per conversion for the entire system. A novel model predicts tracking nonlinearity (NL) in the form of harmonic distortion (HD) for weakly NL (i.e. SFDR>30dBc) first order open-loop sampling circuits. The mechanisms for the NL are exponential settling, amplitude modulation, phase modulation and discrete-time modulation. The model demonstrates that HD typically increases at 20 dB per decade over most standard operating ranges and is a function of input frequency, sampling bandwidth, input amplitude, the sample rate and component nonlinearity. Application of the model is reduced to the equivalent of frequency-independent nonlinearity analysis over this range, requiring only a Taylor series expansion of the NL time constant. Design insight is given for common MOS switch types, revealing a high correlation between HD and bandwidth. The first method to quantify the trade-off between thermal noise (SNR) and linearity (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4, and HD5 versus frequency at multiple sample rates of a Sample and Hold test chip fabricated in a 0.25μm 1P5M CMOS process and Spectre simulation results support the findings. The results broadly apply to switched capacitor circuits in general and sampling circuits specifically, regardless of technology

High-Performance Multi-Antenna Wireless for 5G and Beyond

Over the next decade, multi-antenna radios, including phased array and multiple-input-multiple-output (MIMO) radios, are expected to play an essential role in the next-generation of wireless networks. Phased arrays can reject spatial interferences and provide coherent beamforming gain, and MIMO technology promises to significantly enhance the system performance in the coverage, capacity, and user data rate through the beamforming or diversity/capacity gain which can substantially increase the range in wireless links, that are challenged from the transmitter (TX) power handling, receiver (RX) noise perspectives and a multi-path environment. Furthermore, the multi-user MIMO (MU-MIMO) can simultaneously serve multiple users which is vital for femtocell base stations and access points (AP). Full-duplex (FD) wireless, namely simultaneous transmission and reception at the same frequency, is an emerging technology that has gained attention due to its potential to double the data throughput, as well as provide other benefits in the higher layers such as better spectral efficiency, reducing network and feedback signaling delays, and resolving hidden-node problems to avoid collisions. However, several challenges remain in the quest for the high-performance integrated FD radios. Transmitter power handling remains an open problem, particularly in FD radios that integrate a shared antenna interface. Secondly, FD operation must be achieved across antenna VSWR variations and a changing EM environment. Finally, FD must be extended to multi-antenna radios, including phased array and multi-input multi-output (MIMO) radios, as over the next decade, they are expected to play an essential role in the next generation of wireless networks. Multi-antenna FD operation, however, is challenged not only by the self-interference (SI) from each TX to its own RX but also cross-talk SI (CT-SI) between antennas. In this dissertation, first, a full-duplex phased array circulator-RX (circ.-RX) is proposed that achieves self-interference cancellation (SIC) through repurposing beamforming degrees of freedom (DoF) on TX and RX. Then, an FD MIMO circ.-RX is proposed that achieves SI and CT-SI cancellation (CT-SIC) through passive RF and shared-delay baseband (BB) canceller that addresses challenges associated with FD MIMO operation. Wireless radios at millimeter-wave (mm-wave) frequencies enable the high-speed link for portable devices due to the wide-band spectrum available. Large-scale arrays are required to compensate for high path loss to form an mm-wave link. Mm-wave MIMO systems with digitization enable virtual arrays for radar, digital beamforming (DBF) for high mobility scenarios and spatial multiplexing. To preserve MIMO information, the received signal from each element in MIMO RX should be transported to ADC/DSP IC for DBF, and vice versa on the TX side. A large-scale array can be formed by tiling multiple mm-wave IC front-ends, and thus, a single-wire interface is desired between DSP IC and mm-wave ICs to reduce board routing complexity. Per-element digitization poses the challenge of handling high data-rate I/O in large-scale tiled MIMO mm-wave arrays. SERializer – DESerializer (SERDES) is traditionally being used as a high-speed link in computing systems and networks. However, SERDES results in a large area and power consumption. In this dissertation, a 60~GHz 4-element MIMO TX with a single-wire interface is presented that de-multiplexes the baseband signal of all elements and LO reference that are frequency-domain multiplexed on a single-wire coax cable

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts