Diagonal Kernel Point Estimation of nth-Order Discrete Volterra-Wiener Systems

The estimation of diagonal elements of a Wiener model kernel is a well-known problem. The new operators and notations proposed here aim at the implementation of efficient and accurate nonparametric algorithms for the identification of diagonal points. The formulas presented here allow a direct implementation of Wiener kernel identification up to the th order. Their efficiency is demonstrated by simulations conducted on discrete Volterra systems up to fifth order

Identification of cascade of Hammerstein models for the description of non-linearities in vibrating devices

International audienceIn a number of vibration applications, systems under study are slightly nonlinear. It is thus of great importance to have a way to model and to measure these nonlinearities in the frequency range of use. Cascade of Hammerstein models conveniently allows one to describe a large class of nonlinearities. A simple method based on a phase property of exponential sine sweeps is proposed to identify the structural elements of such a model from only one measured response of the system. Mathematical foundations and practical implementation of the method are discussed. The method is afterwards validated on simulated and real systems. Vibrating devices such as acoustical transducers are well approximated by cascade of Hammerstein models. The harmonic distortion generated by those transducers can be predicted by the model over the entire audio frequency range for any desired input amplitude. Agreement with more time consuming classical distortion measurement methods was found to be good

Characterization of systems for software defined radio

Mestrado em Engenharia Electrónica e TelecomunicaçõesEsta dissertação insere-se na área de electrónica de rádio frequência, mais precisamente na caracterização de sistemas para rádios definidos por software (SDR). Um SDR é aquele que possui a flexibilidade para sintonizar, filtrar, ajustar a taxa de transmissão e controlar o tipo de modulação através de software. O aparecimento de novas tecnologias no mercado obriga à utilização de uma quantidade considerável de hardware nos dispositivos de transmissão/recepção, assim uma solução consiste no uso de arquitecturas de SDR onde a conversão do sinal analógico para digital é executada o mais próximo possível da antena e, sendo depois todo o processamento efectuado digitalmente. Assim, nesta tese, é apresentado um modelo comportamental para receptores de SDR, que leva em conta os elementos chave da distorção não linear. Além disso, são apresentadas algumas comparações entre simulações e medidas usando sinais multi-seno e WiMax usando um receptor ideal de SDR. Finalmente, é proposto um novo sistema de caracterização para dispositivos de SDR. ABSTRACT: This dissertation is related to the radio frequency area, more specifically to the characterization of systems for software-defined radio. A software-defined radio is one that has the flexibility to tune, filter, set the transmission rate and control the modulation type only by software. The emergence of new technologies in the market forces the use of a considerable quantity of hardware in the transceivers systems, so a viable solution for this is to use SDR solutions where the analogue to digital conversion is made closest possible of the antenna and then make all the processing digitally. So, in this dissertation, a behavioral model for SDR front end receiver evaluation, that captures the key elements of the nonlinear distortion, is proposed. Moreover, some comparisons between measured and simulated results under multisine and WiMax excitations are presented using the ideal SDR receiver. Finally, a new instrumentation system for characterization of SDR front ends is proposed

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied

Analysis and design of low-power data converters

In a large number of applications the signal processing is done exploiting both analog and digital signal processing techniques. In the past digital and analog circuits were made on separate chip in order to limit the interference and other side effects, but the actual trend is to realize the whole elaboration chain on a single System on Chip (SoC). This choice is driven by different reasons such as the reduction of power consumption, less silicon area occupation on the chip and also reliability and repeatability. Commonly a large area in a SoC is occupied by digital circuits, then, usually a CMOS short-channel technological processes optimized to realize digital circuits is chosen to maximize the performance of the Digital Signal Proccessor (DSP). Opposite, the short-channel technology nodes do not represent the best choice for analog circuits. But in a large number of applications, the signals which are treated have analog nature (microphone, speaker, antenna, accelerometers, biopotential, etc.), then the input and output interfaces of the processing chip are analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC) both digital and analog circuits can be found. This gives advantages in term of total size, cost and power consumption of the SoC. The specific characteristics of CMOS short-channel processes such as: • Low breakdown voltage (BV) gives a power supply limit (about 1.2 V). • High threshold voltage VTH (compared with the available voltage supply) fixed in order to limit the leakage power consumption in digital applications (of the order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many problems with the stacked topologies. • Threshold voltage dependent on the channel length VTH = f(L) (short channel effects). • Low value of the output resistance of the MOS (r0) and gm limited by speed saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20 to 26dB. • Mismatch which brings offset effects on analog circuits. make the design of high performance analog circuits very difficult. Realizing lowpower circuits is fundamental in different contexts, and for different reasons: lowering the power dissipation gives the capability to reduce the batteries size in mobile devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the life of remote sensing devices, satellites, space probes, also allows the reduction of the size and weight of the heat sink. The reduction of power dissipation allows the realization of implantable biomedical devices that do not damage biological tissue. For this reason, the analysis and design of low power and high precision analog circuits is important in order to obtain high performance in technological processes that are not optimized for such applications. Different ways can be taken to reduce the effect of the problems related to the technology: • Circuital level: a circuit-level intervention is possible to solve a specific problem of the circuit (i.e. Techniques for bandwidth expansion, increase the gain, power reduction, etc.). • Digital calibration: it is the highest level to intervene, and generally going to correct the non-ideal structure through a digital processing, these aims are based on models of specific errors of the structure. • Definition of new paradigms. This work has focused the attention on a very useful mixed-signal circuit: the pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in high-precision applications where a resolution of about 10-16 bits and sampling rates above hundreds of Mega-samples per second (telecommunication, radar, etc.) are needed. An introduction on the theory of pipeline ADC, its state of the art and the principal non-idealities that affect the energy efficiency and the accuracy of this kind of data converters are reported in Chapter 1. Special consideration is put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep submicron technology nodes side effects called short channel effects exist opposed to older technology nodes where undesired effects are not present. An overview of the short channel effects and their consequences on design, and also power consuption reduction techniques, with particular emphasis on the specific techniques adopted in pipelined ADC are reported in Chapter 2. Moreover, another way may be undertaken to increase the accuracy and the efficiency of an ADC, this way is the digital calibration. In Chapter 3 an overview on digital calibration techniques, and furthermore a new calibration technique based on Volterra kernels are reported. In some specific applications, such as software defined radios or micropower sensor, some circuits should be reconfigurable to be suitable for different radio standard or process signals with different charateristics. One of this building blocks is the ADC that should be able to reconfigure the resolution and conversion frequency. A reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply starting from the required conversion frequency was developed, and the results are reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for the feedback loop and its theory is described

Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications

The rapid proliferation of the Internet has been driving communication networks closer and closer to their limits, while available bandwidth is disappearing due to an ever-increasing network load. Over the past decade, optical fiber communication technology has increased per fiber data rate from 10 Tb/s to exceeding 10 Pb/s. The major explosion came after the maturity of coherent detection and advanced digital signal processing (DSP). DSP has played a critical role in accommodating channel impairments mitigation, enabling advanced modulation formats for spectral efficiency transmission and realizing flexible bandwidth. This book aims to explore novel, advanced DSP techniques to enable multi-Tb/s/channel optical transmission to address pressing bandwidth and power-efficiency demands. It provides state-of-the-art advances and future perspectives of DSP as well

Correlation of Signals, Noise, and Harmonics in Parallel Analog-to-Digital Converter Arrays

Combining M analog-to-digital converters (ADC) in parallel increases the maximum signal-to-noise ratio (SNR) by a factor of M, assuming the noise is uncorrelated from one channel to the next. This allows for a significant increase in SNR over a single ADC; however, noise and harmonic correlation degrade this improvement. ADCs have three sources of noise: thermal (and other random physical processes), sampling, and quantization noise. There are two system components creating harmonics: the sampler and the quantizer. In this thesis, I determine, analytically and experimentally, the degree of correlation between signals, noise, and harmonics in a parallel ADC array. To test the analysis experimentally, I developed a 16-channel test-bed using 16-bit, state-of-the-art ADCs and 16 direct-digital synthesizers as low-noise signal sources. The test bed provides excellent signal isolation between channels and minimal digital noise to enable the measurement of very low levels of correlation. I investigated the feasibility of measuring the very high levels of signal correlation in the presence of channel nonlinearities with different measurement signals. For a completely linear channel, the channel matching is limited by noise. With nonlinearities, the ability to measure the signal correlation depends on the measurement signal. I verified that the thermal noise is uncorrelated across 16 channels as expected. I also demonstrated that sampling noise is fully correlated from channel-to-channel when a common clock drives the ADCs. Efforts to reduce the correlation using two previously developed de-correlation techniques-phase randomization and frequency offsets-successfully reduced the correlated noise by a factor of two. I then demonstrated analytically and experimentally that harmonics from quantizers are largely uncorrelated; however, harmonics from the sampler are largely correlated confirming the need for decorrelation techniques. I demonstrated the impact of the previously developed decorrelation techniques to reduce harmonic correlation and developed two new decorrelation techniques: phase cancellation and clock offsets, which offer significant advantages over phase randomization and frequency offsets. Each technique offers different levels of dynamic range improvement and complexity, allowing for a range of techniques to target the optimal level of decorrelation

Optics for AI and AI for Optics

Artificial intelligence is deeply involved in our daily lives via reinforcing the digital transformation of modern economies and infrastructure. It relies on powerful computing clusters, which face bottlenecks of power consumption for both data transmission and intensive computing. Meanwhile, optics (especially optical communications, which underpin today’s telecommunications) is penetrating short-reach connections down to the chip level, thus meeting with AI technology and creating numerous opportunities. This book is about the marriage of optics and AI and how each part can benefit from the other. Optics facilitates on-chip neural networks based on fast optical computing and energy-efficient interconnects and communications. On the other hand, AI enables efficient tools to address the challenges of today’s optical communication networks, which behave in an increasingly complex manner. The book collects contributions from pioneering researchers from both academy and industry to discuss the challenges and solutions in each of the respective fields

Advanced digital predistortion of power amplifiers for mobile and wireless communications

This research work focuses on improving the performances of digital predistorters while maintaining low computational complexity for mobile and wireless communication systems. Initially, the thesis presents the fundamental theory of power amplifiers, overview of existing linearisation and memory-effects compensation techniques and reveals the current issues in the field. Further, the thesis depicts the proposed solutions to the problems, including the developed in-band distortion modelling technique, model extraction methods, memoryless digital predistortion technique based on distortion components iterative injection, baseband equalisation technique for minimising memory effects, Matlab-ADS co-simulation system and adaptation circuit with an offline training scheme. The thesis presents the following contributions of the research work. A generalized in-band distortion modelling technique for predicting the nonlinear behaviour of power amplifiers is developed and verified experimentally. Analytical formulae are derived for calculating predistorter parameters. Two model extraction techniques based on the least-squares regression method and frequency-response analysis are developed and verified experimentally. The area of implementation and the trade-off between the methods are discussed. Adjustable memoryless digital predistortion technique based on the distortion components iterative injection method is proposed in order to overcome the distortion compensation limit peculiar to the conventional injection techniques. A baseband equalisation method is developed in order to provide compensation of memory effects for increasing the linearising performance of the proposed predistorter. A combined Matlab-ADS co-simulation system is designed for providing powerful simulation tools. An adaptation circuit is developed for the proposed predistorter for enabling its adaptation to environmental conditions. The feasibility, performances and computational complexity of the proposed digital predistortion are examined by simulations and experimentally. The proposed method is tuneable for achieving the best ratio of linearisation degree to computational complexity for any particular application

Energy-Efficient Receiver Design for High-Speed Interconnects

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1E−12 at −16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s. Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1E−12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency. Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.</p