Anytime system level verification via parallel random exhaustive hardware in the loop simulation

System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability

QUANTITATIVE SAFETY ASSESSMENT OF AIR TRAFFIC CONTROL SYSTEMS THROUGH SYSTEM CONTROL CAPACITY

Quantitative Safety Assessments (QSA) are essential to safety benefit verification and regulations of developmental changes in safety critical systems like the Air Traffic Control (ATC) systems. Effectiveness of the assessments is particularly desirable today in the safe implementations of revolutionary ATC overhauls like NextGen and SESAR. QSA of ATC systems are however challenged by system complexity and lack of accident data

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Formal methods for functional verification of cache-coherent systems-on-chip

State-of-the-art System-on-Chip (SoC) architectures integrate many different components, such as processors, accelerators, memories, and I/O blocks. Some of those components, but not all, may have caches. Because the effort of validation with simulation-based techniques, currently used in industry, grows exponentially with the complexity of the SoC, this thesis investigates the use of formal verification techniques in this context. More precisely, we use the CADP toolbox to develop and validate a generic formal model of a heterogeneous cache-coherent SoC compliant with the recent AMBA 4 ACE specification proposed by ARM. We use a constraint-oriented specification style to model the general requirements of the specification. We verify system properties on both the constrained and unconstrained model to detect the cache coherency corner cases. We take advantage of the parametrization of the proposed model to produce a comprehensive set of counterexamples of non-satisfied properties in the unconstrained model. The results of formal verification are then used to improve the industrial simulation-based verification techniques in two aspects. On the one hand, we suggest using the formal model to assess the sanity of an interface verification unit. On the other hand, in order to generate clever semi-directed test cases from temporal logic properties, we propose a two-step approach. One step consists in generating system-level abstract test cases using model-based testing tools of the CADP toolbox. The other step consists in refining those tests into interface-level concrete test cases that can be executed at RTL level with a commercial Coverage-Directed Test Generation tool. We found that our approach helps in the transition between interface-level and system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench.Les architectures des systèmes sur puce (System-on-Chip, SoC) actuelles intègrent de nombreux composants différents tels que les processeurs, les accélérateurs, les mémoires et les blocs d'entrée/sortie, certains pouvant contenir des caches. Vu que l'effort de validation basée sur la simulation, actuellement utilisée dans l'industrie, croît de façon exponentielle avec la complexité des SoCs, nous nous intéressons à des techniques de vérification formelle. Nous utilisons la boîte à outils CADP pour développer et valider un modèle formel d'un SoC générique conforme à la spécification AMBA 4 ACE récemment proposée par ARM dans le but de mettre en œuvre la cohérence de cache au niveau système. Nous utilisons une spécification orientée contraintes pour modéliser les exigences générales de cette spécification. Les propriétés du système sont vérifié à la fois sur le modèle avec contraintes et le modèle sans contraintes pour détecter les cas intéressants pour la cohérence de cache. La paramétrisation du modèle proposé a permis de produire l'ensemble complet des contre-exemples qui ne satisfont pas une certaine propriété dans le modèle non contraint. Notre approche améliore les techniques industrielles de vérification basées sur la simulation en deux aspects. D'une part, nous suggérons l'utilisation du modèle formel pour évaluer la bonne construction d'une unité de vérification d'interface. D'autre part, dans l'objectif de générer des cas de test semi-dirigés intelligents à partir des propriétés de logique temporelle, nous proposons une approche en deux étapes. La première étape consiste à générer des cas de tests abstraits au niveau système en utilisant des outils de test basé sur modèle de la boîte à outils CADP. La seconde étape consiste à affiner ces tests en cas de tests concrets au niveau de l'interface qui peuvent être exécutés en RTL grâce aux services d'un outil commercial de génération de tests dirigés par les mesures de couverture. Nous avons constaté que notre approche participe dans la transition entre la vérification du niveau interface, classiquement pratiquée dans l'industrie du matériel, et la vérification au niveau système. Notre approche facilite aussi la validation des propriétés globales du système, et permet une détection précoce des bugs, tant dans le SoC que dans les bancs de test commerciales

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

The Digital Transformation of Automotive Businesses: THREE ARTEFACTS TO SUPPORT DIGITAL SERVICE PROVISION AND INNOVATION

Digitalisation and increasing competitive pressure drive original equipment manufacturers (OEMs) to switch their focus towards the provision of digital services and open-up towards increased collaboration and customer integration. This shift implies a significant transformational change from product to product-service providers, where OEMs realign themselves within strategic, business and procedural dimensions. Thus, OEMs must manage digital transformation (DT) processes in order to stay competitive and remain adaptable to changing customer demands. However, OEMs aspiring to become participants or leaders in their domain, struggle to initiate activities as there is a lack of applicable instruments that can guide and support them during this process. Compared to the practical importance of DT, empirical studies are not comprehensive. This study proposes three artefacts, validated within case companies that intend to support automotive OEMs in digital service provisioning. Artefact one, a layered conceptual model for a digital automotive ecosystem, was developed by means of 26 expert interviews. It can serve as a useful instrument for decision makers to strategically plan and outline digital ecosystems. Artefact two is a conceptual reference framework for automotive service systems. The artefact was developed based on an extensive literature review, and the mapping of the business model canvas to the service system domain. The artefact intends to assist OEMs in the efficient conception of digital services under consideration of relevant stakeholders and the necessary infrastructures. Finally, artefact three proposes a methodology by which to transform software readiness assessment processes to fit into the agile software development approach with consideration of the existing operational infrastructure. Overall, the findings contribute to the empirical body of knowledge about the digital transformation of manufacturing industries. The results suggest value creation for digital automotive services occurs in networks among interdependent stakeholders in which customers play an integral role during the services’ life-cycle. The findings further indicate the artefacts as being useful instruments, however, success is dependent on the integration and collaboration of all contributing departments.:Table of Contents Bibliographic Description II Acknowledgment III Table of Contents IV List of Figures VI List of Tables VII List of Abbreviations VIII 1 Introduction 1 1.1 Motivation and Problem Statement 1 1.2 Objective and Research Questions 6 1.3 Research Methodology 7 1.4 Contributions 10 1.5 Outline 12 2 Background 13 2.1 From Interdependent Value Creation to Digital Ecosystems 13 2.1.1 Digitalisation Drives Collaboration 13 2.1.2 Pursuing an Ecosystem Strategy 13 2.1.3 Research Gaps and Strategy Formulation Obstacles 20 2.2 From Products to Product-Service Solutions 22 2.2.1 Digital Service Fulfilment Requires Co-Creational Networks 22 2.2.2 Enhancing Business Models with Digital Services 28 2.2.3 Research Gaps and Service Conception Obstacles 30 2.3 From Linear Development to Continuous Innovation 32 2.3.1 Digital Innovation Demands Digital Transformation 32 2.3.2 Assessing Digital Products 36 2.3.3 Research Gaps and Implementation Obstacles 38 3 Artefact 1: Digital Automotive Ecosystems 41 3.1 Meta Data 41 3.2 Summary 42 3.3 Designing a Layered Conceptual Model of a Digital Ecosystem 45 4 Artefact 2: Conceptual Reference Framework 79 4.1 Meta Data 79 4.2 Summary 80 4.3 On the Move Towards Customer-Centric Automotive Business Models 83 5 Artefact 3: Agile Software Readiness Assessment Procedures 121 5.1 Meta Data 121 5.2 Meta Data 122 5.3 Summary 123 5.4 Adding Agility to Software Readiness Assessment Procedures 126 5.5 Continuous Software Readiness Assessments for Agile Development 147 6 Conclusion and Future Work 158 6.1 Contributions 158 6.1.1 Strategic Dimension: Artefact 1 158 6.1.2 Business Dimension: Artefact 2 159 6.1.3 Process Dimension: Artefact 3 161 6.1.4 Synthesis of Contributions 163 6.2 Implications 167 6.2.1 Scientific Implications 167 6.2.2 Managerial Implications 168 6.2.3 Intelligent Parking Service Example (ParkSpotHelp) 171 6.3 Concluding Remarks 174 6.3.1 Threats to Validity 174 6.3.2 Outlook and Future Research Recommendations 174 Appendix VII Bibliography XX Wissenschaftlicher Werdegang XXXVII Selbständigkeitserklärung XXXVII

Fundamental Approaches to Software Engineering

This open access book constitutes the proceedings of the 23rd International Conference on Fundamental Approaches to Software Engineering, FASE 2020, which took place in Dublin, Ireland, in April 2020, and was held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020. The 23 full papers, 1 tool paper and 6 testing competition papers presented in this volume were carefully reviewed and selected from 81 submissions. The papers cover topics such as requirements engineering, software architectures, specification, software quality, validation, verification of functional and non-functional properties, model-driven development and model transformation, software processes, security and software evolution