9 research outputs found
Bandwidth-Enhancement gm-C Filter with independent Âżo and Q Tuning Mechanisms in Both Topology and Control Loops
This paper deals with the proposal of a new topology for a gm-C continuous time filter which allows the adjustment and tuning of its characteristic parameters (ÏO and Q) in an independent way (without cross-tuning), thereby extending the Q range of the filter for a particular ÏO value. Additionally a comparison of three different Q-tuning algorithms is presented. It is shown that an LMS-based Q-control strategy allows to overcome the intrinsic dependence between the Q and ÏO tuning loops. The combination of both the proposed filter topology and the selected control loop algorithms results in an enhanced transient performance as well as an improvement in terms of cross-detuning.Postprint (published version
Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors
The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 ”W. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 ”m TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit
Bandwidth-Enhancement gm-C Filter with Independent wo and Q Tuning Mechanisms in Both Topology and Control Loops
This paper deals with the proposal of a new topology for a gm-C continuous time filter which allows the adjustment and tuning of its characteristic parameters (ÏO and Q) in an independent way (without cross-tuning), thereby extending the Q range of the filter for a particular ÏO value. Additionally a
comparison of three different Q-tuning algorithms is presented. It
is shown that an LMS-based Q-control strategy allows to overcome the intrinsic dependence between the Q and ÏO tuning
loops. The combination of both the proposed filter topology and the selected control loop algorithms results in an enhanced transient performance as well as an improvement in terms of cross-detuning.Postprint (published version
Filtro gm-C para aplicaciones de comunicaciones con sintonĂa adaptativa del factor de calidad Q independiente de la sintonĂa de la frecuencia central
Este artĂculo muestra la propuesta de un
filtro gm-C de segundo orden con control
independiente total de la frecuencia central y el factor de calidad diseñado para aplicaciones inalĂĄmbricas multiestĂĄndar. Se presenta asimismo el diseño de los lazos de control adecuados para hacer la correcta sintonĂa del filtro tras una breve descripciĂłn de las ventajas e inconvenientes de las propuestas encontradas en la bibliografĂa. El trabajo se completa con una propuesta de mejora del lazo de control del factor de calidad que permite aumentar la rapidez del lazo y disminuir el error de rizado de la señal de control.Postprint (published version
Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits
High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption.
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth.
Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power.
High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels
Circuits for Analog Signal Processing Employing Unconventional Active Elements
DisertaÄnĂ prĂĄce se zabĂœvĂĄ zavĂĄdÄnĂm novĂœch struktur modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m a smĂĆĄenĂ©m reĆŸimu. FunkÄnost a chovĂĄnĂ tÄchto prvkĆŻ byly ovÄĆeny prostĆednictvĂm SPICE simulacĂ. V tĂ©to prĂĄci je zahrnuta Ćada simulacĂ, kterĂ© dokazujĂ pĆesnost a dobrĂ© vlastnosti tÄchto prvkĆŻ, pĆiÄemĆŸ velkĂœ dĆŻraz byl kladen na to, aby tyto prvky byly schopny pracovat pĆi nĂzkĂ©m napĂĄjecĂm napÄtĂ, jelikoĆŸ poptĂĄvka po pĆenosnĂœch elektronickĂœch zaĆĂzenĂch a implantabilnĂch zdravotnickĂœch pĆĂstrojĂch stĂĄle roste. Tyto pĆĂstroje jsou napĂĄjeny bateriemi a k tomu, aby byla prodlouĆŸena jejich ĆŸivotnost, trend navrhovĂĄnĂ analogovĂœch obvodĆŻ smÄĆuje k stĂĄle vÄtĆĄĂmu sniĆŸovĂĄnĂ spotĆeby a napĂĄjecĂho napÄtĂ. HlavnĂm pĆĂnosem tĂ©to prĂĄce je nĂĄvrh novĂœch CMOS struktur: CCII (Current Conveyor Second Generation) na zĂĄkladÄ BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na zĂĄkladÄ FG, transkonduktor na zĂĄkladÄ novĂ© techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na zĂĄkladÄ GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na zĂĄkladÄ GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na zĂĄkladÄ BD. DĂĄle je uvedeno nÄkolik zajĂmavĂœch aplikacĂ uĆŸĂvajĂcĂch vĂœĆĄe jmenovanĂ© prvky. ZĂskanĂ© vĂœsledky simulacĂ odpovĂdajĂ teoretickĂœm pĆedpokladĆŻm.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.
Analog and Neuromorphic computing with a framework on a reconfigurable platform
The objective of the research is to demonstrate energy-efficient computing on a configurable platform, the Field Programmable Analog Array (FPAA), by leveraging analog strengths, along with a framework, to enable real-time systems on hardware. By taking inspiration from biology, fundamental blocks of neurons and synapses are built, understanding the computational advantages of such neural structures. To enable this computation and scale up from these modules, it is important to have an infrastructure that adapts by taking care of non-ideal effects like mismatches and variations, which commonly plague analog implementations. Programmability, through the presence of floating gates, helps to reduce these variations, thereby ultimately paving the path to take physical approaches to build larger systems in a holistic manner.Ph.D
Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations
Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts.
The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13”m CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18”m CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2.
An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18”m CMOS technology.
Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies