7 research outputs found
Armed Cats: formal concurrency modelling at Arm
International audienceWe report on the process for formal concurrency modelling at Arm. An initial formal consistency model of the Arm achitecture, written in the cat language, was published and upstreamed to the herd+diy tool suite in 2017. Since then, we have extended the original model with extra features, for example mixed-size accesses, and produced two provably equivalent alternative formulations. In this paper, we present a comprehensive review of work done at Arm on the consistency model. Along the way, we also show that our principle for handling mixed-size accesses applies to x86: we confirm this via vast experimental campaigns. We also show that our alternative formulations are applicable to any model phrased in a style similar to the one chosen by Arm
Pattern discovery for parallelism in functional languages
No longer the preserve of specialist hardware, parallel devices
are now ubiquitous. Pattern-based approaches to parallelism,
such as algorithmic skeletons, simplify traditional low-level
approaches by presenting composable high-level patterns of
parallelism to the programmer. This allows optimal parallel
configurations to be derived automatically, and facilitates the
use of different parallel architectures. Moreover, parallel patterns
can be swap-replaced for sequential recursion schemes,
thus simplifying their introduction. Unfortunately, there is no
guarantee that recursion schemes are present in all functional
programs. Automatic pattern discovery techniques can be used
to discover recursion schemes. Current approaches are limited
by both the range of analysable functions, and by the range of
discoverable patterns. In this thesis, we present an approach
based on program slicing techniques that facilitates the analysis
of a wider range of explicitly recursive functions. We then
present an approach using anti-unification that expands the
range of discoverable patterns. In particular, this approach is
user-extensible; i.e. patterns developed by the programmer can
be discovered without significant effort. We present prototype
implementations of both approaches, and evaluate them on
a range of examples, including five parallel benchmarks and
functions from the Haskell Prelude. We achieve maximum
speedups of 32.93x on our 28-core hyperthreaded experimental
machine for our parallel benchmarks, demonstrating
that our approaches can discover patterns that produce good
parallel speedups. Together, the approaches presented in this
thesis enable the discovery of more loci of potential parallelism
in pure functional programs than currently possible.
This leads to more possibilities for parallelism, and so more
possibilities to take advantage of the potential performance
gains that heterogeneous parallel systems present
Recommended from our members
Mechanising and evolving the formal semantics of WebAssembly: the Web's new low-level language
WebAssembly is the first new programming language to be supported natively by all major Web browsers since JavaScript. It is designed to be a natural low-level compilation target for languages such as C, C++, and Rust, enabling programs written in these languages to be compiled and executed efficiently on the Web. WebAssembly’s specification is managed by the W3C WebAssembly Working Group (made up of representatives from a number of major tech companies). Uniquely, the language is specified by way of a full pen-and-paper formal semantics.
This thesis describes a number of ways in which I have both helped to shape the specification of WebAssembly, and built upon it. By mechanising the WebAssembly formal semantics in Isabelle/HOL while it was being drafted, I discovered a number of errors in the specification, drove the adoption of official corrections, and provided the first type soundness proof for the corrected language. This thesis also details a verified type checker and interpreter, and a security type system extension for cryptography primitives, all of which have been mechanised as extensions of my initial WebAssembly mechanisation.
A major component of the thesis is my work on the specification of shared memory concurrency in Web languages: correcting and verifying properties of JavaScript’s existing relaxed memory model, and defining the WebAssembly-specific extensions to the corrected model which have been adopted as the basis of WebAssembly’s official threads specification. A number of deficiencies in the original JavaScript model are detailed. Some errors have been corrected, with the verified fixes officially adopted into subsequent editions of the language specification. However one discovered deficiency is fundamental to the model, an instance of the well-known "thin-air problem".
My work demonstrates the value of formalisation and mechanisation in industrial programming language design, not only in discovering and correcting specification errors, but also in building confidence both in the correctness of the language’s design and in the design of proposed extensions.2019 Google PhD Fellowship in Programming Technology and Software Engineering
Peterhouse Research Fellowshi
Programming Languages and Systems
This open access book constitutes the proceedings of the 31st European Symposium on Programming, ESOP 2022, which was held during April 5-7, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 21 regular papers presented in this volume were carefully reviewed and selected from 64 submissions. They deal with fundamental issues in the specification, design, analysis, and implementation of programming languages and systems
Programming Languages and Systems
This open access book constitutes the proceedings of the 31st European Symposium on Programming, ESOP 2022, which was held during April 5-7, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 21 regular papers presented in this volume were carefully reviewed and selected from 64 submissions. They deal with fundamental issues in the specification, design, analysis, and implementation of programming languages and systems
Programming Languages and Systems
This open access book constitutes the proceedings of the 29th European Symposium on Programming, ESOP 2020, which was planned to take place in Dublin, Ireland, in April 2020, as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020. The actual ETAPS 2020 meeting was postponed due to the Corona pandemic. The papers deal with fundamental issues in the specification, design, analysis, and implementation of programming languages and systems
Recommended from our members
The Semantics of Multicopy Atomic ARMv8 and RISC-V
Previous work has established precise operational concurrency models
for Power and ARMv8, in an abstract micro-architectural style based on
detailed discussion with IBM and ARM staff and extensive hardware
testing. To account for the precise architectural behaviour these
models are complex. This thesis aims to provide a better understanding
for the relaxed memory concurrency models of the architectures ARMv8,
RISC-V, and (to a lesser degree) Power.
Power and early versions of ARMv8 have non-multicopy-atomic (non-MCA)
concurrency models. This thesis provides abstraction results for
these, including a more abstract non-MCA ARMv8 storage subsystem
model, and characterisations of the behaviour of mixed-size Power and
non-MCA ARMv8 programs when using barriers or release/acquire
instructions for all memory accesses, with respect to notions of
Sequential Consistency for mixed-size programs.
During the course of this PhD project, and partly due to our extended
collaboration with ARM, ARM have shifted to a much simplified
multicopy-atomic concurrency architecture that also includes a formal
axiomatic concurrency model. We develop a correspondingly simplified
operational model based on the previous non-MCA models, and, as the
main result of this thesis, prove equivalence between the simplified
operational and the reference axiomatic model.
We have also been actively involved in the RISC-V Memory Model Task
Group. RISC-V has adopted a multicopy atomic model closely following
that of ARMv8, but which incorporates some changes motivated by issues
raised in our operational modelling of ARMv8. We develop an adapted
RISC-V operational concurrency model that is now part of the official
architecture documentation.
Finally, in order to give a simpler explanation of the MCA ARMv8 and
RISC-V concurrency models for programmers, we develop an equivalent
operational concurrency model in a different style. The
\promisingarmriscv model, based on the C11 Promising model, gives up
the micro-architectural intuition the other operational models offer
in favour of providing a more abstract model. We prove it equivalent
to the MCA ARMv8 and RISC-V axiomatic models in Coq.This work was funded by a Computer Laboratory and Qualcomm Premium Studentship, an EPSRC and Arm Ltd. Industrial CASE Studentship (grant no. EP/L505389/1), and the EPSRC Programme Grant “REMS: Rigorous Engineering for Mainstream Systems” (grant no. EP/K008528/1)