Scalable Multiple Patterning Layout Decomposition Implemented by a Distribution Evolutionary Algorithm

As the feature size of semiconductor technology shrinks to 10 nm and beyond, the multiple patterning lithography (MPL) attracts more attention from the industry. In this paper, we model the layout decomposition of MPL as a generalized graph coloring problem, which is addressed by a distribution evolutionary algorithm based on a population of probabilistic model (DEA-PPM). DEA-PPM can strike a balance between decomposition results and running time, being scalable for varied settings of mask number and lithography resolution. Due to its robustness of decomposition results, this could be an alternative technique for multiple patterning layout decomposition in next-generation technology nodes

EDA Solutions for Double Patterning Lithography

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

Algorithms for DFM in electronic design automation

As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit of physics at the expense of design flexibility. On the other hand, IC designs inevitably becomes more complex to meet the increasing demand of computational power. To close this gap, design for manufacturing (DFM) becomes the key to enable an easy and low-cost IC fabrication. Therefore, efficient electronic design automation (EDA) algorithms must be developed for DFM to address the design constraints and help the designers to better facilitate the manufacture process. As the core of manufacturing ICs, conventional lithography systems (193i) reach their limit for the 22 nm technology node and beyond. Consequently, several advanced lithography techniques are proposed, such as multiple patterning lithography (MPL), extreme ultra-violet lithography (EUV), electron beam (E-beam), and block copolymer directed self-assembly (DSA); however, DFM algorithms are essential for them to achieve better printability of a design. In this dissertation, we focus on analyzing the compatibility of designs and various advanced lithography techniques, and develop efficient algorithms to enable the manufacturing. We first explore E-Beam, one of the promising candidates for IC fabrication beyond the 10 nm technology node. To address its low throughput issue, the character projection technique has been proposed, and its stencil planning can be optimized with an awareness of overlapping characters. 2D stencil planning is proved NP-Hard. With the assumption of standard cells, the 2D problem can be partitioned into 1D row ordering subproblems; however, it is also considered hard, and no efficient optimal solution has been provided so far. We propose a polynomial time optimal algorithm to solve the 1D row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Technical proofs and experimental results verify that our algorithm is efficient and indeed optimal. As the most popular and practical lithography technique, MPL utilizes multiple exposures to print a single layout and thus allows placement of features within the minimum distance. Therefore, a feasible decomposition of the layout is a must to adopt MPL, and it is usually formulated as a graph k-coloring problem, which is computationally difficult for k > 2. We study the k-colorability of rectangular and diagonal grid graphs as induced subgraphs of a rectangular or diagonal grid respectively, since it has direct applications in printing contact/via layouts. It remains an open question on how hard it is to color grid graphs due to their regularity and sparsity. In this dissertation, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm for those graphs and conduct experiments to verify its performance and effectiveness. Besides, we also develop an efficient algorithm for model based MPL, because it is more expensive but accurate than the rule based decomposition. As one of the alternative lithography techniques, block copolymer directed self-assembly (DSA) is studied. It has emerged as a low-cost, high- throughput option in the pursuit of alternatives to traditional optical lithography. However, issues of defectivity have hampered DSA’s viability for large-scale patterning. Recent studies have shown the copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density has been demonstrated. In this dissertation, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. We also apply our knowledge in coloring grid graphs to the problem of group-and-coloring in DSA-MPL hybrid lithography. We derive a solution to group-3-coloring and prove the NP-completeness of grouping-2-coloring

Design for Manufacturability in Advanced Lithography Technologies

As the technology nodes keep shrinking following Moore\u27s law, lithography becomes increasingly critical to the fabrication of integrated circuits. The 193nm ArF immersion lithography (193i) has been a common technique for manufacturing integrated circuits. However, the 193i with single exposure has finally reached its printability limit at the 28nm technology node. To keep the pace of Moore\u27s law, design for manufacturability (DFM) is demonstrated to be effective and cost-efficient. The concept of DFM is to modify the design of integrated circuits in order to make them more manufacturable. Tremendous efforts have been made for DFM in advanced lithography technologies. In general, the progress can be summarized in four directions. (1) Advanced lithography process by novel patterning techniques and next-generation lithography; (2) High performance lithography simulation approach in mask synthesis; (3) Physical design (PD) methodology with lithography manufacturability awareness; (4) Robust design flow integrating emerging PD challenges. Accordingly, we propose our research topics in those directions. (1) Throughput optimization for self-aligned double patterning (SADP) and e-beam lithography based manufacturing of 1D layout; (2) Design of efficient rasterization algorithm for mask patterns in inverse lithography technology (ILT); (3) SADP-aware detailed routing; (4) SADP-aware detailed routing with consideration of double via insertion and via manufacturability; (5) Pin accessibility driven detailed placement refinement. In our first research work, we investigate throughput optimization of 1D layout manufacturing. SADP is a mature lithography technique to print 1D gridded layout for advanced technologies. However, in 16nm technology node, trim mask pattern in SADP lithography process may not be printable using 193i along within a single exposure. A viable solution is to complement SADP with e-beam lithography. To order to increase the throughput of 1D layout manufacturing, we consider the problem of e-beam shot minimization subject to bounded line-end extension constraints. Two different approaches of utilizing the trim mask and e-beam to print a 1D layout are considered. The first approach is trimming by end cutting, in which trim mask and e-beam are used to chop up parallel lines at required locations by small fixed rectangles. The second approach is trimming by gap removal, in which trim mask and e-beam are used to rid of all unnecessary portions. We propose elegant integer linear program formulations for both approaches. Experimental results show that both integer linear program formulations can be solved efficiently and have a major speedup compared with previous related work. Furthermore, the pros and cons of the two approaches for manufacturing 1D layout are discussed. In our second research work, we focus on a critical problem of lithography simulation in the design of ILT mask. To reduce the complexity of modern lithography simulation, a widely used approach is to first rasterize the ILT mask before it is inputted to the simulation tool. Accordingly, we propose a high performance rasterization algorithm. The algorithm is based on a pre-computed look-up table. Every pixel in the rasterized image is firstly identified its category: exception or non-exception. Then convolution for every pixel can be performed by a single or multiple look-up table queries depending on its category. In addition, the proposed algorithm has shift invariant property and can be applied for all-angle mask patterns in ILT. Experimental results demonstrate that our approach can speedup conventional rasterization process by almost 500x while maintaining small variations in critical dimension. In our third research work, we concentrate on SADP-aware detailed routing. SADP is a promising manufacturing option for sub-22nm technology nodes due to its good overlay control. To ensure layout is manufacturable by SADP, it is necessary to consider it during layout configuration, e.g., detailed routing stage. However, SADP process is not intuitive in terms of mask design, and considering it during detailed routing stage is even more challenging. We investigate both of two popular types of SADP: spacer-is-dielectric and spacer-is-metal. Different from previous works, we apply the color pre-assignment idea and propose an elegant graph model which captures both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules during detailed routing. A negotiated congestion based rip-up and reroute scheme is applied to achieve good routability while maintaining SADP design rules. Our approach can be extended to consider other multiple patterning lithography during detailed routing, e.g., self-aligned quadruple patterning targeted at sub-10nm technology nodes. Compared with state-of-the-art academic SADP-aware detailed routers, we offer routing solution with better quality of result. In our fourth research work, we extend our SADP-aware detailed routing to consider other manufacturing issues. Both SADP and triple patterning lithography (TPL) are potential layout manufacturing techniques in 10nm technology node. While metal layers can be printed by SADP, via layer manufacturing requires TPL. Previous works on SADP-aware detailed routing do not automatically guarantee via layer are manufacturable by TPL. We extend our SADP-aware detailed routing to consider TPL manufacturability of via layer. Double via insertion is an effective method to improve yield and reliability in integrated circuits manufacturing. We also consider it in our SADP-aware detailed routing to further improve insertion rate. A problem of TPL-aware double via insertion in the post routing stage is proposed. It is solved by both integer linear programming and high-performance heuristic. Experimental results demonstrate that our SADP-aware detailed routing can ensure via layer are TPL manufacturable and improve double via insertion rate. In our last research work, we target at the enhancement of pin access. The significant increased number of routing design rules in advanced technologies has made pin access an emerging difficultly in detailed routing. Resolving pin access in detailed routing may be too late due to the fix pin locations. Thus, we consider pin access in earlier design stage, i.e., detailed placement stage, when perturbation of cell placement is allowed. A cost function is proposed to model pin access for each pin-to-pin connection in detailed routing. A two-phase detailed placement refinement is performed to improve pin access, and refinement techniques are limited to cell flipping, same-row adjacent cell swap and cell shifting. The problem is solved by dynamic programming and linear programming. Experimental results demonstrate that the proposed detailed placement refinement improve pin access and reduce the number of unroutable nets in detailed routing significantly

Spectroscopic investigations of photon-induced reactions in tin-oxo cage photoresists

Molecular compounds such as tin-oxo cages are promising photoresists for Extreme UltraViolet (EUV) photolithography, which is the latest nano-patterning technology for high-end computer chips. Solubility switching of the resist is the key for pattern transfer to the semiconductor substrate. In this thesis, different spectroscopic techniques were used to gain insight into the photochemistry upon exposure, which is crucial for optimizing the resist performance. In one research line, we developed a laser-based high harmonic generation setup as the exposure source in the soft-X-ray (XUV) region to perform broadband absorption spectroscopy on tin-oxo cage samples. Resist-coated thin films were exposed to light with energies of 21 – 70 eV, and the induced changes in the transmission as a function of exposure dose were used to quantify the photoconversion of the resist. The results were compared with those obtained with EUV (92 eV). The resist properties were further investigated using X-ray photoelectron spectroscopy and Total Electron Yield techniques. A synchrotron beamline was used as the exposure source (5-150 eV) to study the low-energy emitted electrons from the resist. Outgassing measurements (residual gas analysis) and ellipsometry techniques were used to investigate the resist’s photoconversion under 92 eV exposure. Outgassing species from the resist were determined to be mainly organic carbon-containing products. The outgassing rate was measured for a few selected masses and the induced resist’s thickness change at different exposure doses was related to the outgassing rate of the resist. The fundamental insight obtained in our studies can help to design improved EUV photoresists

Vat 3D printable materials and post-3D printing procedures for the development of engineered devices for the biomedical field

L'abstract è presente nell'allegato / the abstract is in the attachmen

Reactive inkjet of quantum dot-silicone composites

There is a need for high-resolution and high-sensitivity temperature sensing in fields such as micro/nanoelectronics, integrated photonics, and biomedicine; however, non-invasive integrated sensing is difficult and expensive to achieve in miniaturised devices, as fabrication is greatly complicated by multi-step processes, heat treatments, and material compatibility. Inkjet printing (IJP) is a direct writing technique in the material jetting AM category that is effective for maskless multi-material printing with <50 µm resolution, which enables production of end-use devices and could simplify sensor integration. Existing inkjet-printed temperature sensors comprise simple circuit devices, which use the change in the electrical resistance of a sensing area to measure temperature. While current examples are well-suited to wearable sensors, they do not achieve the spatial and thermal resolutions desired for printed devices such as microfluidics. Development of inks for luminescence nanothermometry would enable inkjet-printable sensing geometries for planar and 3D thermal imaging with submicron and subdegree resolutions. Silicones are polymers suitable for optical sensing due to their ultraviolet (UV) and thermal stability, optical transparency, and high refractive indices. Composite inks for luminescence nanothermometry can be formulated with quantum dots (QDs), fluorescent semiconductor nanocrystals with intrinsic, reversible temperature quenching. Printable optical sensing materials would enable in situ temperature monitoring for applications and geometries that are otherwise impossible to monitor by conventional means. This thesis describes the development of the first inkjet-printable QD-silicone composite, and the first ink for luminescence thermometry, for integrated optical sensing; these may also have use in lighting applications . 2-part addition cure silicone inks and 1-part UV cure silicone inks were explored and QD-silicone composites were synthesised; inkjet printing of an addition cure QD-composite was demonstrated. Printing of reactive addition cure inks, where Ink A contained crosslinker and Ink B contained catalyst, was demonstrated using drop-on-drop IJP with the smallest average drop diameters reported for silicone IJP to date (33 36 µm). To overcome poor contact pinning, a pinned grid strategy was used for single printhead IJP and a line-by-line strategy for dual printhead IJP. Curing was the greatest challenge in reactive inkjet of QD-silicone composites, as labile ligands on the QDs poisoned the platinum catalyst despite low QD loading (0.005 wt% QD-Ink A). PtCl2 catalyst was added at low loading to enable curing and to explore the interactions between QDs and the catalyst. However, quenching was observed, with 70% decrease in emission intensity as PtCl2 concentration doubled; it was theorised that the QDs and catalyst competed for ligands, leading to metal-induced aggregation. Printing of fluorescent QD-silicone composites was demonstrated on a single printhead system using a pinned grid strategy; inks with no PtCl2 had stronger fluorescence but did not cure, highlighting their greater vulnerability to delays or fluctuations in heating. Novel UV curable silicone inks were formulated for inkjet using a high throughput screening method. Two photoinitiators (PIs) were trialled: DMPA (2,2-dimethoxy-2-phenylacetophenone) and TPO (phenylbis(2,4,6-trimethylbenzoyl)-phosphine oxide). DMPA was associated with rapid loss of fluorescence in QD-silicones, whereas quenching was not observed with TPO. Detachment of passivating ligands followed by photo-oxidation was suggested as a mechanism: TPO radicals are more susceptible to recombination with oxygen radicals than DMPA derived radicals, which might result in better shielding of the QD surface. Printing of 1 wt% TPO silicone inks without quantum dots was carried out under nitrogen to prevent oxygen inhibition. Jetting was demonstrated with 34-42 µm average drop diameter on silanised glass slides, while printing of continuous films was demonstrated on glass slides coated in a release agent. The temperature sensing performance of novel QD-silicone composites was assessed via fluorescence spectroscopy and imaging. 100 nm diameter QD clusters were observed in transmission electron microscopy and micron-scale QD aggregates in optical microscopy. QD emission appeared to be largely unchanged by immobilisation in silicone, although QD aggregation was expected to reduce photostability of the composite. Intensity- and spectral shift-based optical thermometry was demonstrated using well-plate reading and confocal laser scanning microscopy. Emission sensitivity at 627 nm was found to be approximately -0.7 to -1.2 % °C-1 between 30 50 °C and spectral sensitivity 0.07 to 0.08 nm °C-1, in agreement with other values in QD-sensing literature. Intensity decreased between thermal cycles of the same sample, although values at 60 °C were unchanged, while spectral shift appeared repeatable without redshift. Overall, fluorescent QD-silicone composites were produced via IJP for the first time and were shown to have temperature-sensitive emission. These materials are suitable for inkjet-printable devices with embedded optical temperature sensors using luminescence nanothermometry