On decoding of multi-level MPSK modulation codes

The decoding problem of multi-level block modulation codes is investigated. The hardware design of soft-decision Viterbi decoder for some short length 8-PSK block modulation codes is presented. An effective way to reduce the hardware complexity of the decoder by reducing the branch metric and path metric, using a non-uniform floating-point to integer mapping scheme, is proposed and discussed. The simulation results of the design are presented. The multi-stage decoding (MSD) of multi-level modulation codes is also investigated. The cases of soft-decision and hard-decision MSD are considered and their performance are evaluated for several codes of different lengths and different minimum squared Euclidean distances. It is shown that the soft-decision MSD reduces the decoding complexity drastically and it is suboptimum. The hard-decision MSD further simplifies the decoding while still maintaining a reasonable coding gain over the uncoded system, if the component codes are chosen properly. Finally, some basic 3-level 8-PSK modulation codes using BCH codes as component codes are constructed and their coding gains are found for hard decision multistage decoding

Implementable Wireless Access for B3G Networks - III: Complexity Reducing Transceiver Structures

This article presents a comprehensive overview of some of the research conducted within Mobile VCE’s Core Wireless Access Research Programme,1 a key focus of which has naturally been on MIMO transceivers. The series of articles offers a coherent view of how the work was structured and comprises a compilation of material that has been presented in detail elsewhere (see references within the article). In this article MIMO channel measurements, analysis, and modeling, which were presented previously in the first article in this series of four, are utilized to develop compact and distributed antenna arrays. Parallel activities led to research into low-complexity MIMO single-user spacetime coding techniques, as well as SISO and MIMO multi-user CDMA-based transceivers for B3G systems. As well as feeding into the industry’s in-house research program, significant extensions of this work are now in hand, within Mobile VCE’s own core activity, aiming toward securing major improvements in delivery efficiency in future wireless systems through crosslayer operation

Trellis phase codes for power-bandwith efficient satellite communications

Support work on improved power and spectrum utilization on digital satellite channels was performed. Specific attention is given to the class of signalling schemes known as continuous phase modulation (CPM). The specific work described in this report addresses: analytical bounds on error probability for multi-h phase codes, power and bandwidth characterization of 4-ary multi-h codes, and initial results of channel simulation to assess the impact of band limiting filters and nonlinear amplifiers on CPM performance

Decoding Schemes for Foliated Sparse Quantum Error Correcting Codes

Foliated quantum codes are a resource for fault-tolerant measurement-based quantum error correction for quantum repeaters and for quantum computation. They represent a general approach to integrating a range of possible quantum error correcting codes into larger fault-tolerant networks. Here we present an efficient heuristic decoding scheme for foliated quantum codes, based on message passing between primal and dual code 'sheets'. We test this decoder on two different families of sparse quantum error correcting code: turbo codes and bicycle codes, and show reasonably high numerical performance thresholds. We also present a construction schedule for building such code states.Comment: 23 pages, 15 figures, accepted for publication in Phys. Rev.

Nested turbo codes for the costa problem

Driven by applications in data-hiding, MIMO broadcast channel coding, precoding for interference cancellation, and transmitter cooperation in wireless networks, Costa coding has lately become a very active research area. In this paper, we first offer code design guidelines in terms of source- channel coding for algebraic binning. We then address practical code design based on nested lattice codes and propose nested turbo codes using turbo-like trellis-coded quantization (TCQ) for source coding and turbo trellis-coded modulation (TTCM) for channel coding. Compared to TCQ, turbo-like TCQ offers structural similarity between the source and channel coding components, leading to more efficient nesting with TTCM and better source coding performance. Due to the difference in effective dimensionality between turbo-like TCQ and TTCM, there is a performance tradeoff between these two components when they are nested together, meaning that the performance of turbo-like TCQ worsens as the TTCM code becomes stronger and vice versa. Optimization of this performance tradeoff leads to our code design that outperforms existing TCQ/TCM and TCQ/TTCM constructions and exhibits a gap of 0.94, 1.42 and 2.65 dB to the Costa capacity at 2.0, 1.0, and 0.5 bits/sample, respectively

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders