On one-way cellular automata with a fixed number of cells

We investigate a restricted one-way cellular automaton (OCA) model where the number of cells is bounded by a constant number k, so-called kC-OCAs. In contrast to the general model, the generative capacity of the restricted model is reduced to the set of regular languages. A kC-OCA can be algorithmically converted to a deterministic finite automaton (DFA). The blow-up in the number of states is bounded by a polynomial of degree k. We can exhibit a family of unary languages which shows that this upper bound is tight in order of magnitude. We then study upper and lower bounds for the trade-off when converting DFAs to kC-OCAs. We show that there are regular languages where the use of kC-OCAs cannot reduce the number of states when compared to DFAs. We then investigate trade-offs between kC-OCAs with different numbers of cells and finally treat the problem of minimizing a given kC-OCA

On decoding of multi-level MPSK modulation codes

The decoding problem of multi-level block modulation codes is investigated. The hardware design of soft-decision Viterbi decoder for some short length 8-PSK block modulation codes is presented. An effective way to reduce the hardware complexity of the decoder by reducing the branch metric and path metric, using a non-uniform floating-point to integer mapping scheme, is proposed and discussed. The simulation results of the design are presented. The multi-stage decoding (MSD) of multi-level modulation codes is also investigated. The cases of soft-decision and hard-decision MSD are considered and their performance are evaluated for several codes of different lengths and different minimum squared Euclidean distances. It is shown that the soft-decision MSD reduces the decoding complexity drastically and it is suboptimum. The hard-decision MSD further simplifies the decoding while still maintaining a reasonable coding gain over the uncoded system, if the component codes are chosen properly. Finally, some basic 3-level 8-PSK modulation codes using BCH codes as component codes are constructed and their coding gains are found for hard decision multistage decoding

Visualization on colour based flow vector of thermal image for movement detection during interactive session

Recently thermal imaging is exploited in applications such as motion and face detection. It has drawn attention many researchers to build such technology to improve lifestyle. This work proposed a technique to detect and identify a motion in sequence images for the application in security monitoring system or outdoor surveillance. Conventional system might cause false information with the present of shadow. Thus, methods employed in this work are Canny edge detector method, Lucas Kanade and Horn Shunck algorithms, to overcome the major problem when using thresholding method, which is only intensity or pixel magnitude is considered instead of relationships between the pixels. The results obtained could be observed in flow vector parameter and the segmentation colour based image for the time frame from 1 to 10 seconds. The visualization of both the parameters clarified the movement and changes of pixel intensity between two frames by the supportive colour segmentation, either in smooth or rough motion. Thus, this technique may contribute to others application such as biometrics, military system, and surveillance machine

A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology

textBinary adders form a major part in various arithmetic logical operation units including multipliers, dividers and digital signal processors. Parallel prefix adders represent a set of efficient structures for binary addition, greatly suited for VLSI implementation due to their regularity and speed. This report is focused on the comparative analysis of 5 major types of parallel prefix adder frameworks namely Kooge-Stone, Knowles adders, Brent-Kung, Han-Carlson and Ladner-Fischer adders implemented in Synopsys's SAED 32nm static CMOS technology operating at 1.05V for 8-bit, 16-bit and 32-bit input vectors based on power, performance and area (PPA) metrics. The process technology is modeled with 9 metal tracks. Power, performance and area metrics based on circuit simulations are used for comparison. The metrics are compared across SAED 32nm and FreePDK 45nm technology to quantify the impact of technology on architecture.Electrical and Computer Engineerin