A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Workshop on Verification and Theorem Proving for Continuous Systems (NetCA Workshop 2005)

Oxford, UK, 26 August 200

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Verification of analog circuits in power-down mode

Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e ComputadoresThe energy efficiency and optimization are two important points of analog circuits. With purpose to reduce the power consumption, most of these circuits are equipped with power-down features, which means the circuits are idle when they are not used. In power-down mode internal nodes can have floating states which results in an increase of the transistor degradation. In this thesis a computer program that checks the node voltage levels and the state of the transistors in power-down mode is presented. The search procedure will ensure that all currents in the paths are safely turned off. The program works just with the structural information of the circuit given into a input file i.e net-list file. No numerical simulation is needed. Experimental results show the efficacy and efficiency in industrial circuits and also the integration with the CADENCE software

DEVELOPMENT AND VERIFICATION OF AUTOMATED FIXTURES FOR FUNCTIONAL TESTING OF SPACE GRADE PRINTED CIRCUIT BOARD ASSEMBLIES

Orbion Space Technology is a developer and manufacturer of electric propulsion systems for military and commercial spacecraft. Orbion’s products include a Power Processing Unit (PPU) which is utilized for power and control of the satellite propulsion system. These PPUs are complex electro-mechanical assemblies that include multiple Printed Circuit Board Assemblies (PCBA) and are built to IPC standards. To ensure smooth fabrication and to reduce the risk of complications from in-process rework of PCBAs, comprehensive electrical functional testing at the board-level is required before higher- level assembly. Electrical functional testing provides verification of quality, workmanship, and manufacturing defects of the PCBAs. The test fixtures detailed in this report are intended for use in a manufacturing line and are rugged, technician-friendly, and capable of meeting Orbion’s testing requirements. This project delivers a functional 200V power supply, a functional automated test fixture, and a design for a second automated test fixture