Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

Supply Current Modeling and Analysis of Deep Sub-Micron Cmos Circuits

Continued technology scaling has introduced many new challenges in VLSI design. Instantaneous switching of the gates yields high current flow through them that causes large voltage drop at the supply lines. Such high instantaneous currents and voltage drop cause reliability and performance degradation. Reliability is an issue as high magnitude of current can cause electromigration, whereas, voltage drop can slow down the circuit performance. Therefore, designing power supply lines emphasizes the need of computing maximum current through them. However, the development of digital integrated circuits in short design cycle requires accurate and fast timing and power simulation. Unfortunately, simulators that employ device modeling methods, such as HSPICE are prohibitively slow for large designs. Therefore, methods which can produce good maximum current estimates in short times are critical. In this work a compact model has been developed for maximum current estimation that speeds up the computation by orders of magnitude over the commercial tools

Statistical static timing analysis considering the impact of power supply noise in VLSI circuits

As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology. In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated. Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis

Performance and power optimization in VLSI physical design

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay

Performance and power optimization in VLSI physical design

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay

Analysis and modeling of power supply induced jitter for high speed driver and low dropout voltage regulator

”With the scaling of power supply voltage levels and improving trans-conductance of drivers, the sensitivity of drivers to power supply induced delays has increased. The power supply induced jitter (PSIJ) has become one of the major concerns for high-speed system. In this work, the PSIJ analysis and modeling method are proposed for high speed drivers and the system with on-die low dropout (LDO) voltage regulator. In addition, a jitter-aware target impedance concept is proposed for power distribution network (PDN) design to correlate the PSIJ with PDN parasitic. The proposed PSIJ analysis model is based on the driver power supply rejection ratio (PSRR) response, transition edge slope and the propagation delay. It is demonstrated that the proposed model can be generalized for different type of drivers. Following the proposed PSIJ model, a method for improving the PSIJ simulation accuracy in the input/output buffer information (IBIS) model is also proposed. A PSIJ analysis method is also proposed for system with on-die LDO. The approach relies on separate analysis of the LDO block PSRR response and the buffer block PSIJ sensitivity. This procedure allows designer to evaluate the system PSIJ with fewer and faster simulations. For the jitter-aware target impedance, a systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. Given the transient IC switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The proposed design procedure can largely relieve over-constrain in the PDN designed based on the original target impedance definition”--Abstract, page iv

Studies on physical interconnect technologies in advanced SoC designs

制度:新 ; 文部省報告番号:甲1992号 ; 学位の種類:博士(工学) ; 授与年月日:2005/3/15 ; 早大学位記番号:新392