Surveyor ejecta detector model ML 256-1 and 185-1 and Surveyor ejecta detector ground support equipment model ML 260-1 Final engineering report

Engineering analyses on Surveyor lunar dust particle detector instrumentation, and ground support equipmen

Exploitation of Unintentional Information Leakage from Integrated Circuits

Unintentional electromagnetic emissions are used to recognize or verify the identity of a unique integrated circuit (IC) based on fabrication process-induced variations in a manner analogous to biometric human identification. The effectiveness of the technique is demonstrated through an extensive empirical study, with results presented indicating correct device identification success rates of greater than 99:5%, and average verification equal error rates (EERs) of less than 0:05% for 40 near-identical devices. The proposed approach is suitable for security applications involving commodity commercial ICs, with substantial cost and scalability advantages over existing approaches. A systematic leakage mapping methodology is also proposed to comprehensively assess the information leakage of arbitrary block cipher implementations, and to quantitatively bound an arbitrary implementation\u27s resistance to the general class of differential side channel analysis techniques. The framework is demonstrated using the well-known Hamming Weight and Hamming Distance leakage models, and approach\u27s effectiveness is demonstrated through the empirical assessment of two typical unprotected implementations of the Advanced Encryption Standard. The assessment results are empirically validated against correlation-based differential power and electromagnetic analysis attacks

A coprocessor for secure and high speed modular arithmetic

We present a coprocessor design for fast arithmetic over large numbers of cryptographic sizes. Our design provides a efficient way to prevent side channel analysis as well as fault analysis targeting modular arithmetic with large prime or composite numbers. These two countermeasure are then suitable both for Elliptic Curve Cryptography over prime fields or RSA using CRT or not. To do so, we use the residue number system (RNS) in an efficient manner to protect from leakage and fault, while keeping its ability to fast execute modular arithmetic with large numbers. We illustrate our countermeasure with a fully protected RSA-CRT implementation using our architecture, and show that it is possible to execute a secure 1024 bit RSA-CRT in less than 0:7 ms on a FPGA

Fault attacks on RSA and elliptic curve cryptosystems

This thesis answered how a fault attack targeting software used to program EEPROM can threaten hardware devices, for instance IoT devices. The successful fault attacks proposed in this thesis will certainly warn designers of hardware devices of the security risks their devices may face on the programming leve

CUDA-Accelerated RNS Multiplication in Word-Wise Homomorphic Encryption Schemes

Homomorphic encryption (HE), which allows computation over encrypted data, has often been used to preserve privacy. However, the computationally heavy nature and complexity of network topologies make the deployment of HE schemes in the Internet of Things (IoT) scenario difficult. In this work, we propose CARM, the first optimized GPU implementation that covers BGV, BFV and CKKS, targeting for accelerating homomorphic multiplication using GPU in heterogeneous IoT systems. We offer constant-time low-level arithmetic with minimum instructions and memory usage, as well as performance- and memory-prior configurations, and exploit a parametric and generic design, and offer various trade-offs between resource and efficiency, yielding a solution suitable for accelerating RNS homomorphic multiplication on both high-performance and embedded GPUs. Through this, we can offer more real-time evaluation results and relieve the computational pressure on cloud devices. We deploy our implementations on two GPUs and achieve up to 378.4×, 234.5×, and 287.2× speedup for homomorphic multiplication of BGV, BFV, and CKKS on Tesla V100S, and 8.8×, 9.2×, and 10.3× on Jetson AGX Xavier, respectively

A microprocessor-based system for protecting busbars

Advancements in digital technology have led to the development of microprocessor-based relays. However, most of these relays use algorithms similar in principle to their electromechanical counterparts. Also, busbar protection using microprocessor-based relays has not received adequate attention unlike other power system components. Few algorithms proposed for protecting busbars lack inherent immunity to current transformer (ct) saturation. They achieve stability by using additional measures, such as, using special circuitry, multiple algorithms and changing the restraint factor, which are not likely to be effective during severe ct saturation. The impact of ct ratio-mismatch is countered by using percentage-bias characteristics that reduces the sensitivity of the relay. This thesis presents a new technique for protecting busbars. The technique uses positive-sequence and negative-sequence models of the power system in a fault-detection algorithm. While phase voltages and currents are used to detect faults, parameters of the power system are not used. Only the arguments of the positive-sequence and negative-sequence impedances computed by the relay are used to make trip decisions. The performance of the technique was investigated for a variety of operating conditions and for several busbar configurations. Data generated by empty simulations of model power systems were used in the investigations. The results verify that the proposed technique is able to distinguish faults in a busbar protection zone from those outside the zone correctly. Additionally, its stability during ct saturation, immunity to ct ratio-mismatch and applicability, without any modifications, to busbars of different configurations have been established. An analysis of the performance of the proposed technique during ct saturation and ratio-mismatch conditions is presented. The effect of various parameters, such as, presence of d.c. offset in the currents, mild and severe saturation of the cts, different sampling frequencies and the impact of the size of data-windows on the estimates of the current phasors have been included. The analysis indicates that the technique is stable during ct saturation and inherently immune to ct ratio-mismatch. The proposed technique was implemented using a general purpose relay hardware. The hardware and software constituents of the prototype, the procedure for testing these relays by using a playback simulator and selected test results are presented in this thesis