Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica

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Program      Length08:00 - 08:45 Registration 0:4508:45 - 09:15 Opening session 0:3009:15 - 10:15 Keynote speech (Richard Marshall, Xitex) 1:00Session chair:10:15 - 11:10 Posters I (coffee break) 0:55Paper #14 Ugo Mureddu, Lilian Bossuet and Viktor FischerA comparison of PUF cores suitable for FPGA devices1528 Thomas Sarno, Romain Wacquez, Philippe Maurine, Khalil Jradi, Jean-Michel Portal, Driss Aboulkassimi, Sarra Souiki-Figuigui, Jérémy Postel-Pellerin, Pierre Canet, Maxime Chambonneau and David GrojoElectromagnetic Analysis Perturbation using Chaos Generator30 Honorio Martin, Giorgio Di Natale and Pedro Peris-LopezPoster: A Self-Repairable TRNG31 Yoav Weizman, Batya Karp and Osnat KerenModeling SRAM cell stability for randomness evaluation of PUF cells42 Linus Feiten, Matthias Sauer and Bernd BeckerUsing LUT-specific delays to mitigate biases in delay-based PUFs and increase area efficiency on FPGAs4811:10 - 12:30 Session I 1:20Session chair:Paper #STSM-1 Ke Jiang Real-Time Scheduling as a Countermeasure Against DPASTSM-2 Maria Méndez Real Investigation on Spatial Isolation against Logical Cache-based Side-Channel Attacks in Multi/Many-Core ArchitecturesSTSM-3 Tania Richmond DPA Aiming the Secret Permutation in the McEliece CryptosystemSTSM-4 Airo Farulla Giuseppe Model Driven Design of Secure Properties for Vision-Based Applications12:30 ‐ 14:30 Lunch 2:00UNDISCLOSEDUNDISCLOSEDMonday	14thTopic: PUFs and TRNGsTopic: STSM presentationsIlia PolianDaniel Arumí     14:30 - 16:10 Session II 1:40Session chair:Paper #5 Oto Petura, Ugo Mureddu, Nathalie Bochard, Lilian Bossuet and Viktor FischerEvaluation of AIS-20/31 compliant TRNG cores implemented on FPGAs12 Raimondo Luzzi, Marco Bucci, Christoph Böhm and Maximiliam HoferA Reliable Low-area Low-power PUF-based Key Generator2041 Christine Utz, Johannes Tobisch and Georg T. BeckerExtended Abstract: Analysis of 1000 Arbiter PUF based RFID Tags5716:10 - 17:30 Posters II (coffee break) 1:20Paper #11 Erica Tena-Sánchez, Salvador Canas, Irene Duran and Antonio AcostaVulnerability Evaluation and Secure Design Methodology of Cryptohardware for ASIC-embedded Secure Applications to Prevent Side-Channel Attacks36 Mosabbah Mushir Ahmed, David Hely, Etienne Perret and Romain SiragusaAuthentication of IC based on Electromagnetic Signature4454 Laurent Sauvage, Youssef Souissi and Sofiane TakarabtSecure Silicon: Towards Virtual Prototyping6029 Jelena Milosevic and Nicolas Sklavos Malware in IoT Hardware Devices17:30 - 20:00 Welcome reception 2:30UNDISCLOSEDUNDISCLOSEDUNDISCLOSEDUNDISCLOSEDTopic: PUFs and TRNGsTopic: Validation and Evaluation / Detection of malicious componentsNele Mentens    Length08:00 - 09:40 Session III 1:40Session chair:Paper #25 Pascal Sasdrich, Amir Moradi and Tim GüneysuHiding Higher-Order Side-Channel Leakage - Randomizing Threshold Implementations in Reconfigurable Hardware40 Florian Wilde, Berndt Gammel and Michael PehlSpatial Correlations in Physical Unclonable Functions51 Viacheslav Izosimov and Martin TörngrenSecurity Evaluation of Cyber-Physical Systems in Society-Critical Internet of Things59 Natalia Mendo, Rubén Nuevo and David HernandezExperimental results on smartcards’ IC EM radiation39 Michael Weiner and Salvador ManichThe SALVADOR simulation framework09:40 - 10:50 Posters III (coffee break) 1:10Paper #10 Francisco Eugenio Potestad-Ordóñez, Carlos Jesus Jiménez-Fernández and Manuel Valencia-BarreroFault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks1322 Apostolos Fournaris, Louiza Papachristodoulou, Lejla Batina and Nicolas SklavosSecure and Efficient RNS Approach for Elliptic Curve Cryptography4650 Shlomo Engelberg and Osnat Keren Trustworthy Communications across Parallel Asynchronous Channels with Glitches21 Madalin Neagu and Salvador Manich Random masking interleaved scrambling technique as a countermeasure for DPA/DEMA attacks in cache memories45 Vojtech Miškovský, Hana Kubatova and Martin NovotnyInfluence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis in FPGA525661 Ofer Hadar, Rami Segal and Raz BirmanH.264 Motion Vectors Based Cyber Defense/Attack TechniquesUNDISCLOSEDUNDISCLOSEDUNDISCLOSEDTuesday	15thTopic: Validation and EvaluationTopic: Fault attack injection, detection and protection / Reconfigurable devices for secure functionsSalvador ManichUNDISCLOSED    10:50 - 12:30 Session IV 1:40Session chair:Paper #7 Jan Burchard, Maël Gay, Jan Horácek, Ange-Salomé Messeng Ekossono, Tobias Schubert, Bernd Becker, Ilia Polian andMartin KreuzerSmall Scale AES Toolbox: Algebraic and Propositional Formulas, Circuit-Implementations and Fault Equations17 Baris Ege, Pedro Maat Massolino and Lejla BatinaSmart Card Fault Injections with High Temperatures24 Juvenal Araujo, Pedro Matutino and Ricardo ChavesResidue Number System Hardware Emulator and Instructions Generator345312:30 ‐ 14:30 Lunch 2:0014:30 - 20:50 Cultural visit and dinner 6:20UNDISCLOSEDUNDISCLOSEDTopic: Fault attack injection, detection and protectionMichael Pehl   Length08:00 - 09:00 Invited speaker (Michael Pehl, EISEC - TUM) 1:00Session chair:09:00 - 10:20 Session V 1:20Session chair:Paper #16 Johanna Sepulveda, Ramon Fernandes, Cesar Marcon and Georg SiglDynamic Security-aware Routing for Zone-based data Protection in Multi-Processor System-on-Chips19 Matej Bartík and Jirí Bucek A Low-Cost Unified Experimental FPGA Board for Cryptography Applications26 Jori Winderickx, Joan Daemen and Nele MentensOn the parallelization of slice-based Keccak implementations on Xilinx FPGAs35 Nicolas Sklavos, Paris Kitsos and Artemios G. VoyiatzisOn the Hardware Implementation Efficiency of CAESAR Authentication Ciphers for FPGA Devices10:20 - 11:10 Posters IV (coffee break) 0:50Paper #6 Marek Laban, Miloš Drutarovský, Viktor Fischer and Michal VarcholaPlatform for testing and evaluation of PUFs and TRNGs implemented in FPGAs9331827 Moshe Avital, Alexander Fish and Osnat KerenFrom Full-Custom to Fully-Standard Cell Power Analysis Countermeasures8 Jo Vliegen, Bob Koninckx, Dave Singelée and Nele MentensReal-time encryption and authentication of medical video streams on FPGA4358 Stjepan Picek, Annelie Heuser, Sylvain Guilley, Domagoj Jakobovic and Nele MentensOn the Machine Learning Techniques for Side-channel Analysis11:10 - 12:30 Session VI 1:20Session chair:Paper #49 Hermann Seuschek, Fabrizio De Santis and Oscar GuillenSide-Channel Leakage Models for IoT Processors23 Arash Nejat, David Hely and Vincent BeroulleReusing Logic Masking to Facilitate Hardware Trojan Detection38 Johanna Baehr and Michael TempelmeierCircuit Clustering Methods for Netlist Reverse Engineering55 Francesco Regazzoni, Georg T Becker and Ilia PolianTrojans in Early Design Steps - An Emerging Threat12:30 ‐ 14:30 Lunch 2:0014:30 - 14:50 Closing session 0:2014:50 - 15:10 MC Meeting Session 0:2015:10 - 17:10 Open meeting follow up for other projects in future 2:00UNDISCLOSEDUNDISCLOSEDTopic: Manufacturing test of secure devices / Reverse engineering countermeasures / Hardware Trojans in IPs and ICsWednesday	16thTopic: Reconfigurable devices for secure functionsTopic: Manufacturing test of secure devices / Reverse engineering countermeasures / Other topicsRosa RodríguezIoana VatajeluCarles FerrerUNDISCLOSEDUNDISCLOSED

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