Empirical Analysis of Electron Beam Lithography Optimization Models from a Pragmatic Perspective

Electron Beam (EB) lithography is a process of focussing electron beams on silicon wafers to design different integrated circuits (ICs). It uses an electron gun, a blanking electrode, multiple electron lenses, a deflection electrode, and control circuits for each of these components. But the lithography process causes critical dimension overshoots, which reduces quality of the underlying ICs. This is caused due to increase in beam currents, frequent electron flashes, and reducing re-exposure of chip areas. Thus, to overcome these issues, researchers have proposed a wide variety of optimization models, each of which vary in terms of their qualitative & quantitative performance. These models also vary in terms of their internal operating characteristics, which causes ambiguity in identification of optimum models for application-specific use cases. To reduce this ambiguity, a discussion about application-specific nuances, functional advantages, deployment-specific limitations, and contextual future research scopes is discussed in this text. Based on this discussion, it was observed that bioinspired models outperform linear modelling techniques, which makes them highly useful for real-time deployments. These models aim at stochastically evaluation of optimum electron beam configurations, which improves wafer’s quality & speed of imprinting when compared with other models. To further facilitate selection of these models, this text compares them in terms of their accuracy, throughput, critical dimensions, deployment cost & computational complexity metrics. Based on this discussion, researchers will be able to identify optimum models for their performance-specific use cases. This text also proposes evaluation of a novel EB Lithography Optimization Metric (EBLOM), which combines multiple performance parameters for estimation of true model performance under real-time scenarios. Based on this metric, researchers will be able to identify models that can perform optimally with higher performance under performance-specific constraints

Algorithms for DFM in electronic design automation

As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit of physics at the expense of design flexibility. On the other hand, IC designs inevitably becomes more complex to meet the increasing demand of computational power. To close this gap, design for manufacturing (DFM) becomes the key to enable an easy and low-cost IC fabrication. Therefore, efficient electronic design automation (EDA) algorithms must be developed for DFM to address the design constraints and help the designers to better facilitate the manufacture process. As the core of manufacturing ICs, conventional lithography systems (193i) reach their limit for the 22 nm technology node and beyond. Consequently, several advanced lithography techniques are proposed, such as multiple patterning lithography (MPL), extreme ultra-violet lithography (EUV), electron beam (E-beam), and block copolymer directed self-assembly (DSA); however, DFM algorithms are essential for them to achieve better printability of a design. In this dissertation, we focus on analyzing the compatibility of designs and various advanced lithography techniques, and develop efficient algorithms to enable the manufacturing. We first explore E-Beam, one of the promising candidates for IC fabrication beyond the 10 nm technology node. To address its low throughput issue, the character projection technique has been proposed, and its stencil planning can be optimized with an awareness of overlapping characters. 2D stencil planning is proved NP-Hard. With the assumption of standard cells, the 2D problem can be partitioned into 1D row ordering subproblems; however, it is also considered hard, and no efficient optimal solution has been provided so far. We propose a polynomial time optimal algorithm to solve the 1D row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Technical proofs and experimental results verify that our algorithm is efficient and indeed optimal. As the most popular and practical lithography technique, MPL utilizes multiple exposures to print a single layout and thus allows placement of features within the minimum distance. Therefore, a feasible decomposition of the layout is a must to adopt MPL, and it is usually formulated as a graph k-coloring problem, which is computationally difficult for k > 2. We study the k-colorability of rectangular and diagonal grid graphs as induced subgraphs of a rectangular or diagonal grid respectively, since it has direct applications in printing contact/via layouts. It remains an open question on how hard it is to color grid graphs due to their regularity and sparsity. In this dissertation, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm for those graphs and conduct experiments to verify its performance and effectiveness. Besides, we also develop an efficient algorithm for model based MPL, because it is more expensive but accurate than the rule based decomposition. As one of the alternative lithography techniques, block copolymer directed self-assembly (DSA) is studied. It has emerged as a low-cost, high- throughput option in the pursuit of alternatives to traditional optical lithography. However, issues of defectivity have hampered DSA’s viability for large-scale patterning. Recent studies have shown the copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density has been demonstrated. In this dissertation, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. We also apply our knowledge in coloring grid graphs to the problem of group-and-coloring in DSA-MPL hybrid lithography. We derive a solution to group-3-coloring and prove the NP-completeness of grouping-2-coloring

Layout decomposition for triple patterning lithography

Nowadays the semiconductor industry is continuing to advance the limits of physics as the feature size of the chip keeps shrinking. Products of the 22 nm technology node are already available on the market, and there are many ongoing research studies for the 14/10 nm technology nodes and beyond. Due to the physical limitations, the traditional 193 nm immersion lithography is facing huge challenges in fabricating such tiny features. Several types of next-generation lithography techniques have been discussed for years, such as {\em extreme ultra-violet} (EUV) lithography, {\em E-beam direct write}, and {\em block copolymer directed self-assembly} (DSA). However, the source power for EUV is still an unresolved issue. The low throughput of E-beam makes it impractical for massive productions. DSA is still under calibration in research labs and is not ready for massive industrial deployment. Traditionally features are fabricated under single litho exposure. As feature size becomes smaller and smaller, single exposure is no longer adequate in satisfying the quality requirements. {\em Double patterning lithography} (DPL) utilizes two litho exposures to manufacture features on the same layer. Features are assigned to two masks, with each mask going through a separate litho exposure. With one more mask, the effective pitch is doubled, thus greatly enhancing the printing resolution. Therefore, DPL has been widely recognized as a feasible lithography solution in the sub-22 nm technology node. However, as the technology continues to scale down to 14/10 nm and beyond, DPL begins to show its limitations as it introduces a high number of stitches, which increases the manufacturing cost and potentially leads to functional errors of the circuits. {\em Triple pattering lithography} (TPL) uses three masks to print the features on the same layer, which further enhances the printing resolution. It is a natural extension for DPL with three masks available, and it is one of the most promising solutions for the 14/10 nm technology node and beyond. In this thesis, TPL decomposition for standard-cell-based designs is extensively studied. We proposed a polynomial time triple patterning decomposition algorithm which guarantees finding a TPL decomposition if one exists. For complex designs with stitch candidates, our algorithm is able to find a solution with the optimal number of stitches. For standard-cell-based designs, there are additional coloring constraints where the same type of cell should be fabricated following the same pattern. We proposed an algorithm that is guaranteed to find a solution when one exists. The framework of the algorithm is also extended to pattern-based TPL decompositions, where the cost of a decomposition can be minimized given a library of different patterns. The polynomial time TPL algorithm is further optimized in terms of runtime and memory while keeping the solution quality unaffected. We also studied the TPL aware detailed placement problem, where our approach is guaranteed to find a legal detailed placement satisfying TPL coloring constraints as well as minimizing the {\em half-perimeter wire length} (HPWL). Finally, we studied the problem of performance variations due to mask misalignment in {\em multiple patterning decompositions} (MPL). For advanced technology nodes, process variations (mainly mask misalignment) have significant influences on the quality of fabricated circuits, and often lead to unexpected power/timing degenerations. Mask misalignment would complicate the way of simulating timing closure if engineers do not understand the underlying effects of mask misalignment, which only exists in multiple patterning decompositions. We mathematically proved the worst-case scenarios of coupling capacitance incurred by mask misalignment in MPL decompositions. A graph model is proposed which is guaranteed to compute the tight upper bound on the worst-case coupling capacitance of any MPL decompositions for a given layout

Angewandte Metrologie für additive Herstellungsverfahren

The fabrication of products by additively building them layer by layer promises exciting possibilities, including realisation of Industry 4.0, sustainability, local manufacturing and a measurement dataset which describes every voxel of the produced part. Measurement methodologies, which can measure such a dataset and interpret the result, are therefore needed. A cost-effective additive manufacturing technique, which can help with the worldwide plastic pollution problem, is Fused Filament Fabrication. This is an open source concept and ideal for adoption by developing economies. Measurement approaches are needed, though, to develop this technology beyond a rapid prototyping and modelling tool, to a functional production solution. This thesis develops cost effective, accessible solutions to improve the material feed mechanism, which is one of the most critical process components. A detailed review of the process steps is given first, which also contributes to this still rapidly developing field. This review includes the motion tool chain, from the stepper motor actuation to the firmware implementation to realise motor control. The feedstock materials and the liquefier design are also presented. Five methods for optimisation of the process are developed and experimentally tested. This includes the optical monitoring of the feed mechanism, which can measure the volumetric flow rate, a method to measure the exit flow rate, a pressure sensor to measure the liquefier state, single print optimisation with design of experiments and a link between the in-process and post process measured data. This is taken further by presenting the Vapour Deposition Fabrication concept, which is like the Dynamic Stencil Lithography process, but realised with a configuration based on the Fused Filament Fabrication electronics and firmware. The design and construction of the first Vapour Deposition Fabrication micro-printer are presented. This thesis finds that rate material addition in additive manufacturing is an important process variable, which needs to be monitored with indirect methods. Furthermore, standardisation is important for additive manufacturing, and this includes how G-codes are interpreted by the printer firmware. Finally, many process parameters must be optimised, and the single print optimisation method shown here is an example method, which can form part of a complete printer development, qualification and conformance solution.Die Fertigung von Produkten durch additives schichtweises Aufbauen verspricht spannende Möglichkeiten, darunter die Umsetzung von Industrie 4.0, Nachhaltigkeit, lokale Fertigung und einen Messdatensatz, der jeden Gitterpunkt des produzierten Teils beschreibt. Es werden daher Messmethoden benötigt, die einen solchen Datensatz messen und das Ergebnis interpretieren können. Eine kostengünstige additive Fertigungstechnik, die bei dem weltweiten Problem der Kunststoffverschmutzung helfen kann, ist Fused Filament Fabrication. Dies ist ein Open-Source-Konzept und ideal für die Verwendung in sich entwickelnden Volkswirtschaften. Um diese Technologie über ein Rapid-Prototyping-Tool hinaus zu einer funktionalen Produktionslösung zu entwickeln, sind jedoch neue Messansätze erforderlich. In dieser Arbeit werden kostengünstige und leicht zugängliche Lösungen zur Verbesserung des Materialzufuhrmechanismus entwickelt. Zunächst wird ein detaillierter Überblick über die Prozessschritte gegeben, was auch zu diesem sich schnell entwickelnden Bereich beiträgt. Diese Übersicht umfasst die Bewegungswerkzeuge vom Schrittmotor-Antrieb bis zur Firmware-Implementierung, um die Motorsteuerung zu realisieren. Fünf Methoden zur Optimierung des Prozesses werden entwickelt und experimentell getestet. Dazu gehören die optische Überwachung des Fördermechanismus, die den Volumenstrom messen kann, eine Methode zur Messung der Austrittsströmungsrate, ein Drucksensor zur Messung des Verflüssigerzustands, eine Druckoptimierung mittles statistische Versuchsplanung sowie eine Verknüpfung zwischen der Messdatenverarbeitung und Auswertung. Dies wird durch die Vorstellung des Konzeptes der physikalischen Gasphasenabscheidung weitergeführt, das dem dynamischen Schablonenlithographieprozess ähnlich ist, jedoch mit einer Konfiguration realisiert wird, die auf der Fused Filament Fabrication-Elektronik basiert. Das Design und die Konstruktion des ersten Vapor Deposition Fabrication-Mikrodruckers werden vorgestellt.Diese Arbeit schlussfolgert, dass der Materialdurchsatz in der additiven Fertigung eine wichtige Prozessvariable ist. Darüber hinaus ist eine Standardisierung wichtig für die additive Fertigung. Dies beinhaltet, wie G-Codes von der Drucker-Firmware interpretiert werden. Schließlich müssen viele Prozessparameter optimiert werden und die hier gezeigte Druckoptimierungsmethode ist ein Beispiel, das Teil einer vollständigen Druckerentwicklungs-, Qualifizierungs- und Konformitätslösung sein kann

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

ITR/PE+SY digital clay for shape input and display

Issued as final reportNational Science Foundatio

Conference on Binary Optics: An Opportunity for Technical Exchange

The papers herein were presented at the Conference on Binary Optics held in Huntsville, AL, February 23-25, 1993. The papers were presented according to subject as follows: modeling and design, fabrication, and applications. Invited papers and tutorial viewgraphs presented on these subjects are included