Polynomial Curve Slope Compensation for Peak-Current-Mode-Controlled Power Converters

Linear ramp slope compensation (LRC) and quadratic slope compensation (QSC) are commonly implemented in peak-current-mode-controlled dc-dc converters in order to minimize subharmonic and chaotic oscillations. Both compensating schemes rely on the linearized state-space averaged model (LSSA) of the converter. The LSSA ignores the impact that switching actions have on the stability of converters. In order to include switching events, the nonlinear analysis method based on the Monodromy matrix was introduced to describe a complete-cycle stability. Analyses on analog-controlled dc-dc converters applying this method show that system stability is strongly dependent on the change of the derivative of the slope at the time of switching instant. However, in a mixed-signal-controlled system, the digitalization effect contributes differently to system stability. This paper shows a full complete-cycle stability analysis using this nonlinear analysis method, which is applied to a mixed-signal-controlled converter. Through this analysis, a generalized equation is derived that reveals for the first time the real boundary stability limits for LRC and QSC. Furthermore, this generalized equation allows the design of a new compensating scheme, which is able to increase system stability. The proposed scheme is called polynomial curve slope compensation (PCSC) and it is demonstrated that PCSC increases the stable margin by 30% compared to LRC and 20% to QSC. This outcome is proved experimentally by using an interleaved dc-dc converter that is built for this work

Nonlinear Analysis and Control of Interleaved Boost Converter Using Real-Time Cycle to Cycle Variable Slope Compensation

Switched-mode power converters are inherently nonlinear and piecewise smooth systems that may exhibit a series of undesirable operations that can greatly reduce the converter's efficiency and lifetime. This paper presents a nonlinear analysis technique to investigate the influence of system parameters on the stability of interleaved boost converters. In this approach, Monodromy matrix that contains all the comprehensive information of converter parameters and control loop can be employed to fully reveal and understand the inherent nonlinear dynamics of interleaved boost converters, including the interaction effect of switching operation. Thereby not only the boundary conditions but also the relationship between stability margin and the parameters given can be intuitively studied by the eigenvalues of this matrix. Furthermore, by employing the knowledge gained from this analysis, a real-Time cycle to cycle variable slope compensation method is proposed to guarantee a satisfactory performance of the converter with an extended range of stable operation. Outcomes show that systems can regain stability by applying the proposed method within a few time periods of switching cycles. The numerical and analytical results validate the theoretical analysis, and experimental results verify the effectiveness of the proposed approach

Stability Study and Nonlinear Analysis of DC-DC Power Converters with Constant Power Loads at the Fast Timescale

Rapidly growing distributed renewable networks make an increasing demand on various types of power converters to feed different loads. Power converters with constant power load are one typical configuration that can degrade the stability of the power conversion system due to the negative impedance characteristic. This paper presents a nonlinear analysis method using the developed complete-cycle solution matrix method by transforming the original linear time-variant system into a summation of segmented linear time-invariant systems. Thus, the stability of the nonlinear system can be studied using a series of the corresponding state transition matrix and saltation matrix. As this derived matrix contains all the comprehensive information relating to the system’s stability, the influence of the constant power load to system’s fast-timescale stability in both continuous conduction mode and the discontinuous conduction mode can be fully investigated and analyzed. The phenomena of fast-timescale instability around switching frequency for power converters with a constant power load are observed and investigated numerically. Finally, experimental results have proven the analysis and verified the effectiveness of the developed method

Stability analysis and control of DC-DC converters using nonlinear methodologies

PhD ThesisSwitched mode DC-DC converters exhibit a variety of complex behaviours in power electronics systems, such as sudden changes in operating region, bifurcation and chaotic operation. These unexpected random-like behaviours lead the converter to function outside of the normal periodic operation, increasing the potential to generate electromagnetic interference degrading conversion efficiency and in the worst-case scenario a loss of control leading to catastrophic failure. The rapidly growing market for switched mode power DC-DC converters demands more functionality at lower cost. In order to achieve this, DC-DC converters must operate reliably at all load conditions including boundary conditions. Over the last decade researchers have focused on these boundary conditions as well as nonlinear phenomena in power switching converters, leading to different theoretical and analytical approaches. However, the most interesting results are based on abstract mathematical forms, which cannot be directly applied to the design of practical systems for industrial applications. In this thesis, an analytic methodology for DC-DC converters is used to fully determine the inherent nonlinear dynamics. System stability can be indicated by the derived Monodromy matrix which includes comprehensive information concerning converter parameters and the control loop. This methodology can be applied in further stability analysis, such as of the influence of parasitic parameters or the effect of constant power load, and can furthermore be extended to interleaved operating converters to study the interaction effect of switching operations. From this analysis, advanced control algorithms are also developed to guarantee the satisfactory performance of the converter, avoiding nonlinear behaviours such as fast- and slowscale bifurcations. The numerical and analytical results validate the theoretical analysis, and experimental results with an interleaved boost converter verify the effectiveness of the proposed approach.Engineering and Physical Sciences Research Council (EPSRC), China Scholarship Council (CSC), and school of Electrical and Electronic Engineerin

Design and control of a bidirectional wireless charging system using GaN devices

Most of the existing wireless power transfer system works in unidirectional with one-direction control signals. This paper presents a bidirectional wireless charging system with duplex communication method, which is not only able to achieve the two-way wireless power transmission, but also transfer control signals bi-directionally. The power circuit operation mode is actively controlled by using the wireless transceiver module which can duplex communication to deliver measured signals remotely. The operational principle is analytically studied in details and is verified by simulation. Finally, a prototype of the bidirectional charging system using GaN devices has been successfully designed and tested. In addition, the measured feedback signals are effectively transmitted to validate the control algorithm

DC-DC Converters - Dynamic Model Design and Experimental Verification

To obtain high performance control of a dc-dc converter, a good model of the converter is needed. The load usually affects the dynamics and one way to take this into consideration is to regard the load as a part of the converter. The load is often the most variable part of this system. If the load current and the output voltage are measured there are good possibilities to obtain a good model of the load on-line. Adaptive control can then be applied to improve the control. In peak current-mode control, the output voltage and the inductor current are measured and utilized for control. In the author's licentiate thesis, analytic models were derived for the case where the load current is also measured and utilized for control. The control-to-output transfer function, the output impedance, and the audio susceptibility were derived for the buck, boost, and buck-boost converters operated in continuous conduction mode in the case of resistive load. The use of load current can be seen as gain scheduling in the case where the load is a resistor. Gain scheduling can be considered a special case of adaptive control. The majority of the results in the licentiate thesis were validated by comparing the frequency responses predicted by the analytic models and switched large-signal simulation models. In this thesis, additional results are presented for the buck converter. Experimental results obtained by means of a network analyzer verify the derived control-to-output transfer function and the audio susceptibility but not the output impedance at low frequencies. In the experimental buck converter there are stray resistances in the inductor, transistor, and diode but these stray resistances were not considered in the licentiate thesis. A new transfer function for the output impedance is derived where these stray resistances are considered and it is in good agreement with the experimental result also at low frequencies. If the current to the output capacitor is measured in addition to the output voltage and the inductor current, the load current can be calculated as the difference between the inductor and capacitor currents in the case of the buck converter. Hence, the measurement of the load current can be replaced by measurement of the capacitor current. If this possibility is utilized and the capacitor current is measured by means of a current transformer, a low-frequency resonance is introduced in the frequency responses according to experimental results. The reason for this resonance is due to the high-pass-filter characteristics of the current transformer. A new analytic model is derived which predicts the resonance

Modeling and Analysis of Power Processing Systems (MAPPS). Volume 1: Technical report

Computer aided design and analysis techniques were applied to power processing equipment. Topics covered include: (1) discrete time domain analysis of switching regulators for performance analysis; (2) design optimization of power converters using augmented Lagrangian penalty function technique; (3) investigation of current-injected multiloop controlled switching regulators; and (4) application of optimization for Navy VSTOL energy power system. The generation of the mathematical models and the development and application of computer aided design techniques to solve the different mathematical models are discussed. Recommendations are made for future work that would enhance the application of the computer aided design techniques for power processing systems

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout

System identification and adaptive current balancing ON/OFF control of DC-DC switch mode power converter

PhD ThesisReliability becomes more and more important in industrial application of Switch Mode Power Converters (SMPCs). A poorly performing power supply in a power system can influence its operation and potentially compromise the entire system performance in terms of efficiency. To maintain a high reliability, high performance SMPC effective control is necessary for regulating the output of the SMPC system. However, an uncertainty is a key factor in SMPC operation. For example, parameter variations can be caused by environmental effects such as temperature, pressure and humidity. Usually, fixed controllers cannot respond optimally and generate an effective signal to compensate the output error caused by time varying parameter changes. Therefore, the stability is potentially compromised in this case. To resolve this problem, increasing interest has been shown in employing online system identification techniques to estimate the parameter values in real time. Moreover, the control scheme applied after system identification is often called “adaptive control” due to the control signal selfadapting to the parameter variation by receiving the information from the system identification process. In system identification, the Recursive Least Square (RLS) algorithm has been widely used because it is well understood and easy to implement. However, despite the popularity of RLS, the high computational cost and slow convergence speed are the main restrictions for use in SMPC applications. For this reason, this research presents an alternative algorithm to RLS; Fast Affline Projection (FAP). Detailed mathematical analysis proves the superior computational efficiency of this algorithm. Moreover, simulation and experiment result verify this unique adaptive algorithm has improved performance in terms of computational cost and convergence speed compared with the conventional RLS methods. Finally, a novel adaptive control scheme is designed for optimal control of a DC-DC buck converter during transient periods. By applying the proposed adaptive algorithm, the control signal can be successfully employed to change the ON/OFF state of the power transistor in the DC-DC buck converter to improve the dynamic behaviour. Simulation and experiment result show the proposed adaptive control scheme significantly improves the transient response of the buck converter, particularly during an abrupt load change conditio

Digital instrumentation for the measurement of high spectral purity signals

Improvements on electronic technology in recent years have allowed the application of digital techniques in time and frequency metrology where low noise and high accuracy are required, yielding flexibility in systems implementation and setup. This results in measurement systems with extended capabilities, additional functionalities and ease of use. The Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs), as the system front-end, set the ultimate performance of the system in terms of noise. The noise characterization of these components will allow performing punctual considerations on the study of the implementation feasibility of new techniques and for the selection of proper components according to the application requirements. Moreover, most commercial platforms based on FPGA are clocked by quartz oscillators whose accuracy and frequency stability are not suitable for many time and frequency applications. In this case, it is possible to take advantage of the internal Phase Locked Loop (PLL) for generating the internal clock from an external frequency reference. However, the PLL phase noise could degrade the oscillator stability thereby limiting the entire system performance becoming a critical component for digital instrumentation. The information available currently in literature, describes in depth the features of these devices at frequency offsets far from the carrier. However, the information close to the carrier is a more important concern for time and frequency applications. In this frame, my PhD work is focused on understanding the limitations of the critical blocks of digital instrumentation for time and frequency metrology. The aim is to characterize the noise introduced by these blocks and in this manner to be able to predict their effects on a specific application. This is done by modeling the noise introduced by each component and by describing them in terms of general and technical parameters. The parameters of the models are identified and extracted through the corresponding method proposed accordingly to the component operation. This work was validated by characterizing a commercially available platform, Red Pitaya. This platform is an open source embedded system whose resolution and speed (14 bit, 125 MSps) are reasonably close to the state of the art of ADCs and DACs (16 bit, 350 MSps or 14 bit, 1 GSps/3GSPs) and it is potentially sufficient for the implementation of a complete instrument. The characterization results lead to the noise limitations of the platform and give a guideline for instrumentation design techniques. Based on the results obtained from the noise characterization, the implementation of a digital instrument for frequency transfer using fiber link was performed on the Red Pitaya platform. In this project, a digital implementation for the detection and compensation of the phase noise induced by the fiber is proposed. The beat note, representing the fiber length variations, is acquired directly with a high speed ADC followed by a fully digital phase detector. Based on the characterization results, it was expected a limitation in the phase noise measurement given by the PLL. First measurements of this implementation were performed using the 150 km-long buried fibers, placed in the same cables between INRiM and the Laboratoire Souterrain de Modane (LSM) on the Italy-France border. The two fibers are joined together at LSM to obtain a 300 km loop with both ends at INRiM. From these results the noise introduced by the digital system was verified in agreement with characterization results. Further test and improvements will be performed for having a finished system which is intended to be used on the Italian Link for Frequency and Time from Turin to Florence that is 642-km long and to its extension in the rest of Italy that is foreseen in the next future. Currently, a higher performance platform is under assessment by applying the tools and concepts developed along the PhD. The purpose of this project is the implementation of a state of the art phasemeter whose architecture is based on the DAC. In order to estimate the ultimate performance of the instrument, the DAC characterization is under development and preliminary measurements are also reported here