Operational Experience with the CMS Pixel Detector

In the first LHC running period the CMS-pixel detector had to face various operational challenges and had to adapt to the rapidly changing beam conditions. In order to maximize the physics potential and the quality of the data, online and offline calibrations were performed on a regular basis. The detector performed excellently with an average hit efficiency above 99% for all layers and disks. In this contribution the operational challenges of the silicon pixel detector in the first LHC run and the current long shutdown are summarized and the expectations for 2015 are discussed.Comment: Pixel2014 Conference proceedin

Results on Proton-Irradiated 3D Pixel Sensors Interconnected to RD53A Readout ASIC

Test beam results obtained with 3D pixel sensors bump-bonded to the RD53A prototype readout ASIC are reported. Sensors from FBK (Italy) and IMB-CNM (Spain) have been tested before and after proton-irradiation to an equivalent fluence of about $1$ $\times$ $10^{16}$ $\text{n}_{\text{eq}}$ cm$^{-2}$ (1 MeV equivalent neutrons). This is the first time that one single collecting electrode fine pitch 3D sensors are irradiated up to such fluence bump-bonded to a fine pitch ASIC. The preliminary analysis of the collected data shows no degradation on the hit detection efficiencies of the tested sensors after high energy proton irradiation, demonstrating the excellent radiation tolerance of the 3D pixel sensors. Thus, they will be excellent candidates for the extreme radiation environment at the innermost layers of the HL-LHC experiments.Comment: Conference Proceedings of VCI2019, 15th Vienna Conference of Instrumentation, February 18-22, 2019, Vienna, Austria. arXiv admin note: text overlap with arXiv:1903.0196

A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner

Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 $\mu{} m$ thick die. The target timing resolution is 30 ps RMS for electrons from the conversion of 511 keV photons. A novel synchronization scheme using a patent-pending TDC is used to allow the synchronization of 1.6 million channels across almost 2000 different chips at picosecond-level. A full-featured demonstrator chip with a 3x10 matrix of 500x500 $\mu{} m^{2}$ pixels was produced to validate each block. Its design and experimental results are presented here

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $\mu$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $\Omega$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $\mu$W/pixel. The main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of the CLICdp collaboratio

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.Comment: 15 pages, 10 figures (11 figure files), submitted to Journal of Instrumentatio

PIXIE III: a very large area photon-counting CMOS pixel ASIC for sharp X-ray spectral imaging

PIXIE III is the third generation of very large area (32 x 25 mm(2)) pixel ASICs developed by Pixirad Imaging Counters s. r. l. to be used in combination with suitable X-ray sensor materials (Silicon, CdTe, GaAs) in hybrid assemblies using flip-chip bonding. A Pixirad unit module based on PIXIE III shows several advances compared to what has been available up to now. It has a very broad energy range (from 2 to 100 keV before full pulse saturation), high speed (100 ns peaking time), high frame rate (larger than 500 fps), dead-time-free operation, good energy resolution (around 2 keV at 20 keV), high photo-peak fraction and sharp spectral separation between the color images. In this paper the results obtained with PIXIE III both in a test bench set-up as well in X-ray imaging applications are discussed

Operational experience with the CMS pixel detector

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Energy characterization of Pixirad-1 photon counting detector system

This work is focused on the characterization of the Pixirad-1 detector system from the spectroscopic point of view. An energy calibration has been carried out using different X-ray sources such as fluorescence lines, synchrotron radiation and radioactive elements. The energy resolution has been measured as function of the energy and the results have been compared with theoretical estimation. Last, the charge sharing fraction has been evaluated by exploiting the monochromatic energy of the Elettra synchrotron beam