2,154 research outputs found
Least-Squares Approximation and Polyphase Decomposition for Pipelining Recursive filters
Current techniques used in pipelining recursive filters require high hardware complexity. These techniques attempt to preserve the exact frequency response of the original circuit while seeking to construct a pipelined architecture. We present a technique that relaxes the need to preserve the exact frequency response and instead considers a least-squares formulation in conjunction with the pipelined architecture. The benefit of this design is that it reduces the complexity of the pipelined circuit immensely, while enabling a simple pipelined architecture based on a polyphase decomposition of the original filter
Fast H.264 intra prediction for network video processing
This letter proposes a fast parallel and deeply pipelined architecture for realtime H. 264 intra 4x4 prediction capable of handling up to 32 High Definition video streams (1920x1080 @ 30 fps) simultaneously, while offering high flexibility and consuming only a fraction of resources available on modern FPGA's. The design has been validated on target using a state of the art Altera Stratix IV FPGA
Asynchronous Circuit Stacking for Simplified Power Management
As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture
Auto-Generation of Pipelined Hardware Designs for Polar Encoder
This paper presents a general framework for auto-generation of pipelined
polar encoder architectures. The proposed framework could be well represented
by a general formula. Given arbitrary code length and the level of
parallelism , the formula could specify the corresponding hardware
architecture. We have written a compiler which could read the formula and then
automatically generate its register-transfer level (RTL) description suitable
for FPGA or ASIC implementation. With this hardware generation system, one
could explore the design space and make a trade-off between cost and
performance. Our experimental results have demonstrated the efficiency of this
auto-generator for polar encoder architectures
- …