Phillips SA8016BW 2.5 GHz Synthesizer SEE Testing

This viewgraph presentation reviews the Single Event Effects (SEE) testing of the Phillips SA8016BW 2.5 GHz Synthesizer that was chose by the GLAST Program for Frequency Generation. Included in this are diagrams of the phased-locked loop (PLL), the synthesizer, and heater

Phase error statistics of a phase-locked loop synchronized direct detection optical PPM communication system

Receiver timing synchronization of an optical Pulse-Position Modulation (PPM) communication system can be achieved using a phased-locked loop (PLL), provided the photodetector output is suitably processed. The magnitude of the PLL phase error is a good indicator of the timing error at the receiver decoder. The statistics of the phase error are investigated while varying several key system parameters such as PPM order, signal and background strengths, and PPL bandwidth. A practical optical communication system utilizing a laser diode transmitter and an avalanche photodiode in the receiver is described, and the sampled phase error data are presented. A linear regression analysis is applied to the data to obtain estimates of the relational constants involving the phase error variance and incident signal power

Application of a Simplified PLL Algorithm for Unbalanced Three Phase Systems by Using Low Cost Microcontrollers

In literature, there are many Phased Locked Loop (PLL) methods achieving grid matching successfully under unbalanced grid conditions. However, these methods require high computational resources. In this article, a simplified PLL algorithm has been used with fixed point arithmetic for detecting phase and magnitude of an unbalanced three phase system. The simplification factor comes from the fact that an easy to implement low pass filtering algorithm has been implemented in a 16 bit microcontroller operating at 20 MHz clock speed. Sampling frequency has been selected as 20 kHz so that a low cost grid connected inverter operating up to 20 kHz switching frequency can be designed

A high power CMOS class-D amplifier for inductive-link medical transmitters

Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used thanks to their high efficiency at high frequencies. The initial specifications driving this work require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip phased-locked loop (PLL), a dead-time generator and a phase detector. The PA has been designed in a 0.18μm CMOS high-voltage process technology and occupies an area of 9.86 mm2. It works at frequencies up to 14 MHz and 30 V supply and efficiencies higher than 80% are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimises power delivery to medical implants

On the design of software and hardware for a WSN transmitter

Software defined radios (SDR) are booming. However, for a final breakthrough these systems need to be versatile, inexpensive and easy to program. In this paper a next step is taken to meet all these requirements. Our hardware consists of a computer with an affordable data acquisition (DAQ) card and a cheap self-made single-stage up-converter. The software is written in the slow learning-curve graphical programming environment LabVIEW. To prove the versatility of our SDR transmitter concept, we send packets with the wireless sensor networks (WSN) protocol IEEE 802.15.4, which are received by an existing packet sniffer

Inverter current control for reactive power compensation in solar grid system using Self-Tuned Fuzzy Logic Controller

The solar photovoltaic (PV) systems have gained more attention in renewable energy production due to their cost efficiency and reliability. Typically, reactive power compensation and harmonics elimination are challenging and demanding tasks for improving the efficacy of grid-connected solar PV systems. For this purpose, many research works developed different converter and controller topologies for solving the power quality issues in grid-PV systems. But, it limits the problems of increased harmonics, computation complexity, inefficiency and reduced performance outcomes. Thus, this research aims to develop an integrated hysteresis current controller and Self-Tuned Fuzzy Logic (SFLC) based MPPT controllers for eliminating the harmonics and unbalanced current in single-phase grid systems. Also, it helps to extract the maximum amount of power from the solar PV array. The LUO converter is deployed to reduce ripple contents. The Phased Locked Loop (PLL) based synchronization is performed to maintain the phase angle, frequency and magnitude levels of source power. Moreover, the hysteresis current controller for the inverter has been specifically designed to reduce the THD of the system under IEEE519_1992 regulations. During experiments, both the simulation and hardware results have been evaluated for validating the performance of the proposed controller design

Improving long line stability by integrating renewables using static synchronous generators

Postprint (author's final draft

Demonstration of sustained and useful converter responses during balanced and unbalanced faults in microgrids

In large power grids where converter penetration is presently low and the network impedance is predominantly reactive, the required response from converters during faults is presently specified by phrases such as “maximum reactive output”. However, in marine and aero power systems most faults are unbalanced, the network impedance is resistive, and converter penetration may be high. Therefore a balanced reactive fault current response to an unbalanced fault may lead to over-voltages or over/under frequency events. Instead, this paper presents a method of controlling the converter as a balanced voltage source behind a reactance, thereby emulating the fault response of a synchronous generator (SG) as closely as possible. In this mode there is a risk of converter destruction due to overcurrent. A new way of preventing destruction but still providing fault performance as close to a SG as possible is presented. Demonstrations are presented of simulations and laboratory testing at the 10kVA 400V scale, with balanced and unbalanced faults. Currents can be limited to about 1.5pu while still providing appropriate unbalanced fault response within a resistive network

Synchronous power controller merits for dynamic stability improvement in long line by renewables

Postprint (author's final draft