A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators

© 2017 World Scientific Publishing Company.In this work, a novel circuit structure for second-harmonic multi-phase voltage controlled oscillator (MVCO) is presented. The proposed MVCO is composed of (Formula presented.) ((Formula presented.) being an integer number and (Formula presented.)2) identical inductor–capacitor ((Formula presented.)) tank VCOs. In theory, this MVCO can provide 2(Formula presented.) different phase sinusoidal signals. A six-phase VCO based on the proposed structure is designed in a TSMC 0.18(Formula presented.)um CMOS process. Simulation results show that at the supply voltage of 0.8(Formula presented.)V, the total power consumption of the six-phase VCO circuit is about 1(Formula presented.)mW, the oscillation frequency is tunable from 2.3(Formula presented.)GHz to 2.5(Formula presented.)GHz when the control voltage varies from 0(Formula presented.)V to 0.8(Formula presented.)V, and the phase noise is lower than (Formula presented.)128(Formula presented.)dBc/Hz at 1(Formula presented.)MHz offset frequency. The proposed MVCO has lower phase noise, lower power consumption and more outputs than other related works in the literature.Peer reviewedFinal Accepted Versio

The Effect of DC Component on CMOS Injection-Coupled LC Quadrature Oscillator (IC-QO)

This paper creates a different insight to improve phase noise of Injection-Coupled quadrature oscillators (QOs). In fact, there are several phase noise functions and the important parameter is carrier power that considered here. The QO is analyzed and the mismatches between LC tanks that are the main proofs of phase error in this oscillator are shown. The main aim of this paper is focused on the reduction of phase noise by considering DC term. It is shown that the DC level which ignored in the most previous works is also important to improve phase noise by the carrier power. With due attention in the previous equations the phase noise can be reduced and the phase error can be cancelled or controlled by adjusting bias current. On the other hand as a result, is obtained that increasing of the drain current and the voltage of LC tank decrease the phase noise and the phase error simultaneously. To confirm the proposed idea and analysis, a 5.5 GHz QO is designed and simulated using 0.18µm TSMC CMOS technology. The simulation results show confirmation of the proposed idea

Concepts and methods in optimization of integrated LC VCOs

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results

Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results. A prototype for the QVCO was implemented in a 0.35-/spl mu/m CMOS process with three standard metal layers. The QVCO could be tuned between 1.64 and 1.97 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply. The equivalent phase error between I and Q signals was at most 0.25/spl deg/

A time-variant analysis of the 1/f^(2) phase noise in CMOS parallel LC-Tank quadrature oscillators

This paper presents a study of 1/f/sup 2/ phase noise in quadrature oscillators built by connecting two differential LC-tank oscillators in a parallel fashion. The analysis clearly demonstrates the necessity of adopting a time-variant theory of phase noise, where a more simplistic, time-invariant approach fails to explain numerical simulation results even at the qualitative level. Two topologies of 5-GHz parallel quadrature oscillators are considered, and compact but nevertheless highly general, closed-form formulas are derived for the phase noise caused by the losses in the LC-tanks and by the noisy currents in the MOS transistors. A large number of spectreRF simulations, covering a wide range of working conditions for the oscillators, is used to validate the theoretical analysis

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Comparison of low power, wide tuning range 5 GHz quadrature phase LC CMOS VCO with different devices for resonant circuit

Three low power 5 GHz LC cross-couple quadrature VCO with different resonant circuits were designed and fabricated in a standard 0.18[Mu]m single-poly, six metal layer mixed-signal CMOS process. Combination pairs of an active inductor, spiral inductor, junction varactor and MOScap are used to make the resonant circuit of the quadrature VCO in order to have the best possible performance circuit. Active inductor used in the design is a simple common-source amplifier structure with a PMOS feedback while the passive inductor used is a spiral inductor design using two of the highest level of metal in the process. Junction varactors used in the resonant circuit made use of the capacitance of NWELL and P-implant. All three VCO\u27s have the same topology structure, which is the LC cross-coupled structure. This architecture is used in the design because of the simplicity while the cross-coupled featured will minimize the phase noise of the oscillator. Output drivers and pre-drivers are design to drive the VCO to a 50 ohm load. Phase noise, power dissipation, output power, spectrum accuracy and quadrature phase error are looked for and tested both in the simulation and on chip. Results of all three different types of resonant circuit VCO\u27s are compared and discuss. All the circuits were fabricated through the MOSIS Educational Program